Sense amplifiers with output buffers and memory devices...

Details Sense amplifiers with output buffers and memory devices... Sense amplifiers with output buffers and memory devices...

2005-06-14

2005-06-14

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189090, C365S189050

Reexamination Certificate

active

06906974

ABSTRACT:
A memory device includes a memory cell array including a plurality of memory cells and cell select circuitry configured to selectively connect the plurality of memory cells to a data line, e.g., a common output node of a column selecting gate circuit. The device further includes a bias circuit operative to charge the data line to a bias voltage responsive to a bias enable signal, and a sense amplifier circuit having an input coupled to the data line and including an output buffer. The sense amplifier circuit is operative to drive the output buffer according to a voltage on the data line responsive to a sense enable signal to thereby generate a sense amplifier output signal indicative of a state of a memory cell connected to the data line.

REFERENCES:
patent: 4507759 (1985-03-01), Yasui et al.
patent: 4805143 (1989-02-01), Matsumoto et al.
patent: 5757809 (1998-05-01), Kiso et al.
patent: 6229739 (2001-05-01), Poplevine et al.

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