Sense amplifier with zero power idle mode

Details Sense amplifier with zero power idle mode Sense amplifier with zero power idle mode

1998-04-22

1999-10-05

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Differential sensing

36518905, 36518909, 365194, 365233, G11C 700

Patent

active

059634960

ABSTRACT:
A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.

REFERENCES:
patent: 5459689 (1995-10-01), Hikichi
patent: 5563527 (1996-10-01), Diba
patent: 5594681 (1997-01-01), Taguchi

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