Sense amplifier with positive feedback and self-biasing to achie

Electronic digital logic circuitry – Interface – Supply voltage level shifting

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326 80, 326 31, 326 34, 327 51, 330100, H03K 190175

Patent

active

054537045

ABSTRACT:
A level shift amplifier has first to n th inverters connected in series, with each positive voltage terminal of the first to n th inverter is connected to the first source line. Each negative voltage terminal of the first to (n-2)th inverter is connected to output of the second next inverter, respectively. The negative voltage terminal of the (n-1)th inverter is connected to a part of the output of the n th inverter, and the negative voltage terminal of the n th inverter is connected to the second source line. n pieces of feedback elements are connected between the input and output of each inverter. When a feedback element is established so that the gain of each inverter can be maximized, a self-bias amplifier circuit is composed. All inverters are driven by the self-bias voltage. The fine amplitude signals input to the first inverter become the output voltage of full amplitude between the first and second source lines in the n-th inverter. Also, a positive feedback circuit is composed, and the amplification factor of the level shift amplifier is enhanced.

REFERENCES:
patent: 4794282 (1988-12-01), Colles
patent: 4916337 (1990-04-01), Leung et al.
patent: 4978870 (1990-12-01), Chen et al.
patent: 5045730 (1991-09-01), Cooperman et al.
patent: 5113097 (1992-05-01), Lee
"3.5ns 0.5.mu.m BiCMOS Register File, Design of 3.5ns 0.5 .mu.m BiCMOS Register File", Watanabe et al, The Institute of Electronics, Information and Communication Engineers, Spring National Convention, C-567, 1992, pp. 5-188.
"A 4-Mb CMOS SRAM with a PMOS Thin-Film-Transistor Load Cell", Ootani et al, IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1082-1092.

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