Sense amplifier with override write circuitry

Details Sense amplifier with override write circuitry Sense amplifier with override write circuitry

2002-09-17

2004-06-29

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S145000, C365S205000

Reexamination Certificate

active

06757206

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to improved apparatus and methods for coupling local IO lines with sense amplifiers for accessing ferroelectric and other type memory cells in memory devices.
BACKGROUND OF THE INVENTION
Ferroelectric memory devices, like other semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) cell configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically include one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage.
The ferroelectric memory cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of platelines and wordlines by address decoding circuitry. Such devices are typically organized internally into blocks, sections, segments, rows and columns. For example, a 64M device may include 8 blocks of 8M each, the blocks each consisting of 8 sections which contain 32 segments, Each segment contains 512 words or rows of 64 bits or columns per word. When a data word is read, the cell data from the corresponding bit in each of the 64 columns is sensed using 64 individual sense amplifiers associated with the individual data cell columns.
Data in a ferroelectric data cell is read by connecting the cell capacitor on a first bitline and a reference voltage on a complementary bitline to the input terminals of a differential sense amp. The plateline of the accessed cell is then pulsed. This provides a differential voltage on the bitline pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between a voltage (V
“0”
) associated with a capacitor charged to a binary “0” and that of the capacitor charged to a binary “1” (V
“1”
). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is amplified and applied to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local IO lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device.
In a typical ferroelectric memory read sequence, two sense amp terminals or bitlines are initially equalized to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp terminals via the bitline to which the cell is connected. Thereafter, a reference voltage is connected to the remaining sense amp terminal, and the sense amp senses the differential voltage across the terminals and latches a voltage indicative of whether the target cell was programmed to a binary “0” or to a “1”. The sense amp terminals are then coupled to local IO lines, which were previously precharged to a predetermined voltage state, such as VDD. The sense amp drives one of the local IO lines to a different voltage state, by which the read data state is passed to an IO buffer circuit. In a write operation, the sense amp and bitline terminals are connected to the local IO lines, which are driven to opposite voltage states depending on the data to be written. One bitline connects to the ferroelectric memory cell for storage of the data written into the ferroelectric capacitor.
FIGS. 1 and 2
illustrate a ferroelectric memory device
2
organized in a folded bitline architecture, wherein a segment portion of the device
2
has 512 rows (words) and 64 columns (bits) of data storage cells C
ROW-COLUMN
, where each column of cells is accessed via a pair of complimentary data bitlines BL
COLUMN
and BL
COLUMN
′. One column of the device
2
is illustrated in
FIG. 2
, in which cells C
1
-
1
through C
1
-
64
form a data word accessible via a wordline WL
1
and complimentary bitline pairs BL
1
/BL
1
′ through BL
64
/BL
64
′. The cell data is sensed during data read operations using sense amp circuits
12
(S/A C
1
through S/A C
64
) associated with columns
1
through
64
, respectively. In a typical folded bitline architecture ferroelectric memory device, the cells C
ROW-COLUMN
individually include one or more ferroelectric cell capacitors and one or more access transistors to connect the cell capacitors between one of the complimentary bitlines associated with the cell column and a plateline, where the other bitline is selectively connected to a reference voltage.
In the device
2
, the sense amps
12
associated with even numbered columns are located at the bottom of the segment, whereas sense amps
12
associated with odd numbered columns are located at the top of the segment. Shared reference generators
8
′ and
8
are provided at the top and bottom of the segment columns, respectively. An even column reference generator
8
is provided at the bottom of the segment columns for providing a reference voltage for even numbered columns and an odd column reference generator
8
′ is provided at the top of the columns for the odd numbered columns. The reference voltages from the generators
8
,
8
′ are coupled to one of the bitlines in the columns using one of a pair of switches
8
a
,
8
b
, depending upon whether an even or odd numbered wordline is selected. In reading the first data word of the illustrated segment along the wordline WL
1
in the device
2
, the cells C
1
-
1
through C
1
-
64
are connected to the sense bitlines BL
1
, BL
2
. . . , BL
63
, and BL
64
while the complimentary reference bitlines BL
1
′, BL
2
′ . . . , BL
63
′, and BL
64
′ are floating. The reference bitlines BL
1
′, BL
2
′ . . . BL
63
′, and BL
64
′ are thereafter connected to the reference voltage generators
8
,
8
′.
As illustrated in
FIG. 2
, the ferroelectric memory cells
4
include capacitors C
FE
constructed with ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor C
FE
in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
In ferroelectric memories, as well as conventional DRAMs, the connection of local IO lines LIO/LIO′ to the sense amp terminals SABL/SABL′ is timed during read operations to occur a certain time after the connection of the sense amp terminals SABL/SABL′ to the memory cell
4
and the reference
8
. This is done to prevent disturbance in the sensing operation of the sense amp
12
, where the data bitlines BL
1
/BL
1
′ are initially separated by only a small voltage difference (e.g., tens or hundreds of millivolts). In this regard, the local IO lines, which are precharged at the beginning of the read operation, are typically fairly large in capacitance. As a result, charge from the local IO lines is provided to the sense amp terminals upon connection therewith, which may disturb the amplification operation in the sense amp if connected before sufficient amplification has occurred, leading to degradation of sense margin, and possibly to incorrect data being provided to the local IO buffering circuitry (data polarity flipping). Thus, the timing of LIOS is

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