Sense amplifier with multiple bits sharing a common reference

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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C365S189030, C365S189050, C365S189070, C365S207000

Reexamination Certificate

active

11422774

ABSTRACT:
A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.

REFERENCES:
patent: 6269040 (2001-07-01), Reohr et al.
patent: 6600690 (2003-07-01), Nahas et al.
patent: 6946882 (2005-09-01), Gogi et al.
patent: 2006/0044907 (2006-03-01), Forbes et al.
patent: 2006/0285406 (2006-12-01), Pan et al.
Edward K. S. Au, et al., A Novel Current-Mode Sensing Scheme for Magnetic Tunnel Junction MRAM, IEEE, vol. 40, No. 2, Mar. 2004, pp. 483-488.
T. M. Maffitt, et al., Design Considerations for MRAM, IBM J. Res. & Dev., vol. 50, No. 1, Jan. 2006, pp. 25-39.

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