Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
1996-07-01
2001-06-19
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S208000, C365S189050
Reexamination Certificate
active
06249469
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit memories and particularly relates to sense amplifiers for use therein.
BACKGROUND OF THE INVENTION
Integrated circuit memories include a large number of memory cells which are usually set forth in an array. The memory cells may be volatile or non-volatile. If they are volatile, they may be static RAM cells or dynamic RAM cells. There may be one large array, or a given memory chip may have several sub-arrays which may be arranged in blocks. Typically, the memory device comprises a large number of bit lines extending in one direction. The bit lines may be paired or non paired. Where they are paired, they are often referred to as complementary bit lines, or paired bit lines. Complementary bit lines are used for both static RAM and dynamic RAM applications. The bit lines generally extend in a first direction, and a plurality of word lines extend in a second direction which is perpendicular to the first direction. Typically, a memory cell is located at or near the crossing of a bit line with a word line.
Often, a memory array is divided into subarrays, and each subarray may further be divided into blocks. Each subarray will often have its own “peripheral circuitry” such as decoders.
The memory array or subarray is usually said to be organized into rows and columns. Generally, a row indicates the memory cells located along (coupled to) a word line. A column is therefore ordinarily perpendicular to a row and generally indicates a collection of memory cells along (coupled to) a bit line or a bit line pair. Generally, each column is connected to a respective sense amplifier. One job of the sense amplifier is to sense the effect that the memory cell has on the bit line(s) and to amplify that signal for outputting in a read operation. Conversely, the sense amplifier may also drive or control the bit line(s) when the memory is writing data into a memory cell.
CMOS technology is prevalent today.
FIG. 1
illustrates a prior art configuration and shows a sense amplifier
10
using CMOS technology. The operation and configuration of such a sense amplifier
10
is well known and will not be explained except briefly herein. Amplifier
10
contains P channel transistors
12
and
14
having source electrodes commonly coupled to a line
16
which carries from time to time a signal LP also called LATCHP. The sense amplifier also comprises a pair of N channel transistors
18
,
20
having source electrodes commonly coupled to a line
22
which sometimes carries a signal which may be called LN or LATCHN. A pair of internal nodes A, B are connected to gate electrodes. In particular, node A is coupled to the gate electrodes of transistors
12
and
18
, while node B is coupled to the gate electrodes of transistors
14
and
20
. These transistors form a latch. A first bit line BL
1
on the left side of sense amplifier
10
is coupled to node B which is also coupled between the drain electrode of P channel transistor
12
and the drain electrode of N channel transistor
18
. Likewise, a complementary bit line BL
1
BAR is connected to node A which is also coupled between the drain electrodes of P channel transistor
14
and N channel transistor
20
. Transistors
12
and
14
are referred to as “pull-up” transistors whereas transistors
18
and
20
are referred to as “pull-down” transistors. When a transistor
24
is turned on, it couples VCC through its source-drain path to line
16
, thereby providing the LATCHP signal. Sense amplifier
10
forms a flip-flop so that either transistor
12
or
14
but not both will be turned on and will pull the voltage at its corresponding node toward VCC. At or near the same time, one of the transistors
18
or
20
will pull down the voltage at the other node toward VSS which will be connected to line
22
via a transistor
26
being turned on. In this way, one of the two nodes is pulled high and the other is pulled low, and the sense amplifier latches into a stable state.
In any large memory, such as a 16 megabit DRAM, there will be thousands of columns and thousands of rows. This is represented in
FIG. 1
which shows a second sense amplifier
30
connected to corresponding bit line pair BL
2
and BL
2
BAR, and an N-th sense amplifier
32
coupled to bit lines BLN and BLN BAR. It should be appreciated that N may be on the order of 1000 or more. The LATCHP signal is applied to all N of these sense amplifiers via line
16
, and the LATCHN signal is applied to them via the line
22
. It will be seen in
FIG. 1
that a plurality of resistances
34
are illustrated. These are not discrete resistance devices but rather indicate the parasitic resistance of the lines
16
and
22
, which, even though they are formed of conductive materials such as metal or the like, nevertheless over great distances will have some resistance value. Over each resistance, there will be a voltage drop from the voltage applied via transistor
24
or
26
, as the case may be. Accordingly, the voltage that eventually reaches sense amplifier
32
may be appreciably diminished from VCC or VSS, and that sense amplifier will work inefficiently or slowly. It will also be appreciated that because of this problem, sense amplifier
10
does not activate at the same time as sense amplifier
32
and the resulting skew prolongs access time. Additionally, some prior art designs can be unstable if the selected sense amplifier is connected to the data line (the bit lines) too early.
Thus, as power supply (VSS) line
22
is trying to pull down to 0v, transistors start to turn on in the sense amplifiers. A current flows to the right on line
22
, and there exists a voltage drop due to the resistance of line
22
. Practical limitations prevent the solution of greatly widening line
22
to reduce its resistance—the chip area is jealously allocated. Hence, in the illustrated architecture, the right-most sense amplifier
10
turns on first, and sense amplifier
32
will turn on thereafter.
Generally, one desires to pull down line
22
at a controlled rate. The far end (most remote from transistor
26
) of line
22
will drop in voltage slower than the near end. This slows the memory, which is undesirable, but if circuitry drove the near end too fast, then the corresponding near sense amplifiers would become unreliable.
Another problem occurs when the near sense amplifiers latch logic “1's” and the far amplifier latches a logic “0.” There is a pattern sensitivity because when the bit lines are precharged to ½ VCC, the memory cell moves only one of the bit lines lower or higher. Sensing a “1” occurs before sensing a “0” because LN needs to drop only 1 Vt below a voltage level corresponding to a “1.” However, to sense a “0” LN must be 1Vt below ½ VCC, and this occurs later. Large current flows when “1's” are read. Because of the large currents, the decline in voltage at the far end of line
22
slows to an uncontrolled rate. This effectively can add 7 nsec. to the sensing process —a substantial and undesirable increase.
One approach that has been proposed for addressing this problem is depicted in FIG.
2
. It shows the same sense amplifiers
10
,
30
, and
32
, and has the same signals LATCHP and LATCHN provided by transistors
24
and
26
respectively. However, further N channel transistors have been added beneath the sense amplifiers and a modification has been made so that LATCHN is carried by two distinct lines. One of these lines
40
is constructed relatively wide to carry most of the current, and the other line
42
is relatively narrower because it will carry current for just a single selected sense amplifier. Line
40
is coupled to the sources of a plurality of transistors
44
, each sense amplifier having a respective transistor
44
. Each transistor
44
has its gate electrode coupled to VCC and is therefore generally on. Transistors
44
are relatively small in size so that they do not carry much current to any single sense amplifier.
The narrower line or rail
42
is coupled to the several sense am
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
United Memories Inc.
Zarabian A.
LandOfFree
Sense amplifier with local sense drivers and local read... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sense amplifier with local sense drivers and local read..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sense amplifier with local sense drivers and local read... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2487235