Sense amplifier with adaptive reference generation

Details Sense amplifier with adaptive reference generation Sense amplifier with adaptive reference generation

2003-04-25

2004-08-03

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S203000, C365S208000, C365S210130

Reexamination Certificate

active

06771551

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to sense amplifiers for memory cells and more particularly relates reference voltage generators for such sense amplifiers.
When a memory cell is not differential (such as in a flash memory or other dense memory), a sense amplifier for the cell has to determine the value of a bit stored in the cell by monitoring a single bit line coming out of the cell. Such a sense amplifier needs a reference to trigger the digital value in the cell. This threshold can be generated by well-known techniques, such as using “half-cells” or a fixed or adaptive reference voltage. In some applications, it is desirable to have a reference voltage that is a fixed percentage of a supply voltage to assure some tracking.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
One apparatus embodiment of the invention is useful in a digital memory system including a memory cell arranged to store charge. In such an environment, an adaptive reference voltage can be generated by providing apparatus comprising a bit line coupled to the cell and arranged to conduct a current based on the charge stored in the cell, a transfer gate, a reference voltage generator arranged to generate a reference voltage, a sense amplifier and a control circuit. The control circuit is operative during a first mode of operation to precharge the bit line to generate a bit line precharge voltage and to cause the transfer gate to sample and store the precharge voltage, operative during a second mode of operation to cause the transfer gate to isolate the bit line from the reference voltage generator, to cause the reference voltage generator to generate the reference voltage in response to the sampled and stored precharge voltage and to couple the bit line and the reference voltage to the sense amplifier, and operative during a third mode of operation to isolate the sense amplifier from the bit line and the reference voltage and to energize the sense amplifier to generate an output voltage derived from charge stored in the memory cell and the reference voltage.
One method embodiment of the invention is useful in a digital memory system including a memory cell arranged to store charge and a bit line. In such an environment, an adaptive reference voltage can be generated by a method comprising precharging the bit line to generate a bit line precharge voltage and sampling and storing the bit line precharge voltage. The bit line is isolated from the sampled and stored bit line precharge voltage. A reference voltage is generated in response to the sampled and stored precharge voltage. The bit line and the reference voltage are coupled to the sense amplifier so that the sense amplifier receives a voltage based on charge stored in the memory cell. The sense amplifier is isolated from the bit line and the reference voltage and the sense amplifier is energized to generate an output voltage derived from the charge stored in the memory cell and the reference voltage.
By using the foregoing techniques, a reference voltage for a sense amplifier can be generated with noise suppression characteristics previously unattainable.


REFERENCES:
patent: 5963484 (1999-10-01), Jung
patent: 6411557 (2002-06-01), Terzioglu et al.
patent: 6566913 (2003-05-01), Dai

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