Sense amplifier organization for twin cell memory devices

Details Sense amplifier organization for twin cell memory devices Sense amplifier organization for twin cell memory devices

2008-01-29

2008-01-29

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S172000, C365S189020

Reexamination Certificate

active

07324396

ABSTRACT:
A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain intersections of wordlines and bitlines. A plurality of sense amplifiers are provided, each of which is connected to at least a first pair of bitlines to detect a voltage difference on the bitlines caused by the charge from a twin storage cell comprised of first and second storage cells at the intersection of a single wordline with said first pair of bitlines, respectively. As a result, each cell of a twin storage cell can be accessed with a single wordline.

REFERENCES:
patent: 6522590 (2003-02-01), Matsui et al.
patent: 6768686 (2004-07-01), Frey
patent: 6785157 (2004-08-01), Arimoto et al.
patent: 6914837 (2005-07-01), Schroeder et al.
patent: 6992343 (2006-01-01), Miyatake et al.
patent: 2006/0098508 (2006-05-01), Choi et al.

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