Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-09-04
2002-08-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S190000, C365S233100, C365S194000, C365S195000, C365S196000
Reexamination Certificate
active
06434074
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to memory circuits and, in particular, to self timed memories. Still more particularly, the present invention provides a method and apparatus for sense amplifier imbalance compensation for memory self time circuits.
2. Description of the Related Art
Many computer devices operate based on an external clock. For example, a processor may receive a clock input and perform all operations or events only when the clock transitions. Devices in which events proceed based on a clock transition are referred to as “synchronous” devices. Other computer devices do not base their operation on an external clock. These devices are referred to as “asynchronous” or “self timed” devices. A memory is an example of a device that can be implemented as a self timed device. A self timed memory typically receives a request from a processor (e.g., a read or write request). The memory array then performs the operation and indicates to the processor when the operation is complete. However, the time required for the operation to complete is not based on an external clock (i.e., a predetermined number of clock cycles). Rather, the time required is based on the asynchronous delay paths through the device, which may vary in duration based on the operations that are performed.
The central part of a memory is the memory cell array. Today's memory devices typically include at least one memory cell array organized in rows and columns of memory cells, with each row of memory cells being connected to a distinct word line and each column of memory cells being connected to a distinct bit line or bit line pair. Address decode circuitry is included to select a word line based upon the value of the address provided to the memory device. A distinct sense amplifier (amp) is connected to each pair of bit lines and amplifies the differential voltage placed thereon from accessing a memory cell. The sense amplifiers connected to the bit lines of the memory cells are referred to as “real sense amps.”
A self timed memory device may include a dummy bit that is used to indicate when an operation is completed. A sense amplifier is then connected to the pair of bit lines for the dummy bit. The sense amplifier amplifies the signal and returns this signal to the control logic of the memory device to turn off the sense amps of the memory cell array. The sense amplifier is said to be “sensing” or “looking for” a state. However, due to analog sense amplifier imbalance, a sense amplifier may favor one state and be slow at determining the other state. Due to the manner in which the memory chip is fabricated, all sense amplifiers may be imbalanced uniformly. Thus, if the sense amplifier for the dummy bit is looking for a first state and one of the memory cells stores a second state, the sense amplifier for the dummy bit may sense the first state before the real sense amplifier for the memory cell senses the second state.
Prior art methods for solving the problem of sense amplifier imbalance add margin to the self timing path to slow down the self timed sense amplifier by a fixed delay. However, these prior art methods do not track with any imbalance that may be present in the sense amplifiers associated with the memory cells due to processing, layout mismatches, etc. Therefore, it would be advantageous to provide an improved method and apparatus for sense amplifier imbalance compensation for memory self time circuits.
SUMMARY OF THE INVENTION
The present invention provides a mechanism for self timing a memory circuit to compensate for sense amplifier imbalance. The self timing mechanism comprises two self timed sense amplifiers. A first self timed sense amplifier reads a first state and a second self timed sense amplifier reads a second state. The control logic deactivates the real sense amplifiers in response to the slower of the two self timed sense amplifiers. Thus, even if there is a layout or processing variance, which causes the sense amplifiers to have a non-zero offset voltage and favor a certain output state when the inputs are equal, the real sense amplifiers are able to read the states of the memory cell.
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Carstens Yee & Cahoon LLP
Tran Andrew Q.
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