Electronic digital logic circuitry – Accelerating switching
Patent
1995-06-07
1996-07-30
Westin, Edward P.
Electronic digital logic circuitry
Accelerating switching
327 51, 327374, H03K 1901
Patent
active
055415261
ABSTRACT:
The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are connected along the common signal line between the input pull down transistors and an output. A feedback element connects an output of the second inverter to an input of the first inverter. The inverters are configured to maintain the input of the first inverter at a first intermediate voltage level of V.sub.cc -2 Vt. Input signals received by the input transistors cause the voltage on the signal line to be pulled from the first intermediate level toward Vss. The first inverter responds by generating an output signal which swings from a low voltage of V.sub.ss towards a second intermediate level of V.sub.cc -0.7 Vt. The second inverter responds by generating an output signal which swings between the high level of V.sub.cc and a low level of V.sub.ss. The feedback element includes a time delay, whereby output signals provided by the second inverter are input to the first inverter subject to a time delay. Both method and apparatus embodiments of the invention are disclosed. Furthermore, a particular circuit embodiment is disclosed.
REFERENCES:
patent: 4249095 (1981-02-01), Hau
patent: 4918341 (1990-04-01), Galbraith et al.
patent: 5113097 (1992-05-01), Lee
patent: 5162679 (1992-11-01), Shen et al.
Calogero Stephen
Sun Microsystems Inc.
Westin Edward P.
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