Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-09-14
2001-05-08
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S205000, C365S208000, C365S210130, C365S227000
Reexamination Certificate
active
06229739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to sense amplifiers and, more particularly, to a sense amplifier that has a bias circuit with a reduced size.
2. Description of the Related Art
A dynamic random access memory (DRAM) cell is a memory device that retains data stored in the cell for only a short period of time even when power is continuously applied to the cell. As a result, a DRAM cell must be periodically refreshed to maintain the data stored in the cell.
FIG. 1
shows a cross-sectional diagram that illustrates a conventional DRAM cell
100
. As shown in
FIG. 1
, DRAM cell
100
includes an access transistor
102
which is formed in a p-type material
110
, and a capacitor
104
which is connected to transistor
102
.
Access transistor
102
, in turn, includes spaced-apart source and drain regions
112
and
114
which are formed in material
110
, and a channel region
116
which is defined between regions
112
and
114
. In addition, transistor
102
also includes an access gate
120
which is insulatively formed over channel region
116
.
As further shown in
FIG. 1
, capacitor
104
includes a lower plate
124
which is connected to drain region
114
, a dielectric layer
126
which is formed over lower plate
124
, and an upper plate
128
which is formed over dielectric layer
126
.
In operation, a logic “one” is written to DRAM cell
100
by first placing a programming voltage, such as five volts, on source region
112
while a storage voltage, such as five volts, is applied to the top plate
128
of capacitor
104
and ground is applied to material
110
. The storage voltage (which is continuously applied to top plate
128
) attracts electrons to the lower plate
124
of capacitor
104
where the electrons begin to accumulate.
After placing a programming voltage on source region
112
, access gate
120
is pulsed with an access voltage. This pulse turns on access transistor
102
which causes the electrons on the lower plate
124
of capacitor
104
to flow to source region
112
.
The electrons flow from the lower plate
124
of capacitor
104
to source region
112
because the lower plate
124
of capacitor
104
has a potential which is less than five volts (some cf the applied voltage is dropped across dielectric layer
126
), while source region
112
is at five volts.
When the trailing edge of the pulse again turns off access transistor
102
, a positive potential is stored on the lower plate
124
of capacitor
104
due to the decreased number of electrons which are present on the lower plate
124
of capacitor
104
.
This positive potential, however, lasts only a short time because electrons from leakage currents are readily attracted to the positive potential. As a result, the positive charge stored on the lower plate
124
of capacitor
104
must be “refreshed” by periodically removing the electrons from the lower plate
124
of capacitor
104
.
DRAM cell
100
is erased (a logic “zero” is written to a DRAM cell which already has a logic “one” stored in the cell) by placing ground on source region
112
. Once ground has been applied to source region
112
, access gate
120
is again pulsed with the access voltage.
This pulse turns on access transistor
102
which causes the electrons in source region
112
to flow to the lower plate
124
of capacitor
104
. The electrons flow from source region
112
to the lower plate
124
of capacitor
104
because the lower plate
124
of capacitor
104
has a greater potential than source region
112
.
When the trailing edge of the pulse again turns off access transistor
102
, the positive potential stored on the lower plate
124
of capacitor
104
is removed due to the increased number of electrons which are again present on the lower plate
124
of capacitor
104
.
Due to the overhead required to refresh DRAM cells, large numbers of DRAM cells like cell
100
are typically grouped together to form a memory array.
FIG. 2
shows a schematic diagram that illustrates a conventional DRAM array
200
.
As shown in
FIG. 2
, DRAM array
200
includes a plurality of DRAM cells
100
which are formed in rows and columns in two segments S
1
and S
2
. As further shown in
FIG. 2
, array
200
also includes a plurality of first bit lines BL
1
-BLm and a plurality of second bit lines BLC
1
-BLCm.
The first bit lines BL
1
-BLm are formed adjacent to the columns of cells in first segment S
1
so that each bit line BL is connected to all of the source regions
112
in a column of cells. Similarly, the second bit lines BLC
1
-BLCm are formed adjacent to the columns of cells in second segment S
2
so that each bit line BLC is connected to all of the source regions
112
in a column of cells.
Array
200
further includes a plurality of first word lines WL
1
-WLn and a plurality of second word lines WLC
1
-WLCn. The first word lines WL
1
-WLn are formed adjacent to the rows of cells in first segment S
1
so that each word line WL is connected to all of the access gates
120
in a row of cells. Similarly, the second word lines WL
1
-WLn are formed adjacent to the rows of cells in second segment S
2
so that each word line WLC is connected to all of the access gates
120
in a row of cells.
As additionally shown in
FIG. 2
, array
200
includes a sense circuit
210
which has a plurality of sense amplifiers SA
1
-SAm that are connected to the bit lines BL
1
-BLm and BLC
1
-BLCm so that each sense amplifier SA is connected to a bit line from each segment S
1
and S
2
.
Each sense amplifier SA includes a first invertor which is formed from transistors M
1
and M
3
, and a second invertor which is formed from transistors M
2
and M
4
. In addition, each sense amplifier SA also includes a power switch transistor M
5
and a ground switch transistor M
6
.
Each power switch transistor M
5
provides power to a sense amplifier SA when a first turn on voltage is applied to a power switch line PSL, while each ground switch transistor M
6
connects ground to a sense amplifier SA when a second turn on voltage is applied to a ground switch line GSL.
In operation, a cell is programmed by placing a programming voltage, such as five volts, on the bit line that corresponds with the cell to be programmed, while ground is applied to the remaining bit lines. (A storage voltage, such as five volts, is continuously applied to the top plate
128
of each capacitor
104
and ground is applied to material
110
.)
After placing a programming voltage on the bit line, the word line that corresponds with the cell to be programmed is pulsed with an access voltage while ground is applied to the remainder of the word lines. This pulse turns on the access transistor
102
which causes the electrons on the lower plate
124
of capacitor
104
to flow to source region
112
.
For example, if cell A in
FIG. 2
is to be programmed, the programming voltage is applied to bit line BL
1
while ground is applied to bit lines BL
2
-BLm and BLC
1
-BLCm. In addition, word line WL
1
is pulsed with the access voltage while word lines WL
2
-WLn and WLC
1
-WLCn are connected to ground.
To read a row of cells, ground is placed on the bit lines in the segment that contain the row of cells to be read, while a logic high voltage is placed on the bit lines in the remaining segment. (Since the sense amplifiers SA are based on cross-coupled inverters, the logic states on the bit lines in one segment are always the opposite of the logic states on the bit lines in the other segment.) Once the voltages have been placed on the bit lines, the bit lines are isolated so that the bit lines are only connected to the sense amplifiers SA.
After this, a read voltage, such as five volts, is applied to the word line that corresponds to the row of cells to be read, while ground is applied to the remainder of the word lines. If a cell in the row is storing a logic zero, nothing happens.
On the other hand, if a cell in the row is storing a logic one, the positive potential on the capacitor in the cell raises the voltage on the bit line which, in turn, caus
Bergemont Albert
Kalnitsky Alexander
Poplevine Pavel
National Semiconductor Corporation
Nguyen Viet Q.
Pillsbury & Winthrop LLP
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