Sense amplifier for reduction of access device leakage

Details Sense amplifier for reduction of access device leakage Sense amplifier for reduction of access device leakage

2003-02-18

2004-04-27

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000, C365S149000

Reexamination Certificate

active

06728152

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor memory devices. More particularly, this invention relates to a memory device which includes a sense amplifier circuit that reduces access device leakage during active refresh.
BACKGROUND OF THE INVENTION
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, typically store data in an array of memory cells. Each cell in the array stores a single bit of data (i.e., a logic one or zero) as a charge on a capacitor. For example, referring to
FIG. 1
, a DRAM memory cell or memory bit
100
consists of one MOS transistor
102
and one storage capacitor
104
-accordingly referred to as a one-transistor one-capacitor (1T1C) cell. Memory bit transistor
102
operates as a switch, interposed between the memory bit capacitor
104
and a digit or bit line
106
. Memory bit
100
is capable of holding a single piece of binary information as stored electric charge in capacitor
104
. Given a bias voltage of Vcc/2 on capacitor
104
's common node, a logic one level is represented by +Vcc/2 volts across the capacitor, and a logic zero is represented by −Vcc/2 volts across the cell capacitor. Thus, the potential at node
110
typically equals Vcc for logic one, and ground for logic zero.
Digit line
106
consists of a conductive trace or line connected to a multitude of memory bit transistors for a multitude of memory cells in an array. Generally, either metal or silicided/polycided polysilicon forms the conductive line. Due to the large quantity of attached memory bits, its physical length, and its proximity to other features, digit line
106
is very capacitive. For instance, a typical value for digit line capacitance on a 0.35 um process might be around 300 fF. Digit line capacitance is an important parameter since it dictates many other aspects of the memory design.
Memory bit transistor
102
's gate terminal connects to a word line (row line)
108
. Word line
108
, which also connects to a multitude of memory bits or memory cells, consists of an extended segment of the same polysilicon that is used to form the transistor
102
's gate. Word line
108
is formed so as to be physically orthogonal to digit line
106
. A memory array
200
, as in
FIG. 2
, is created by tiling a selected quantity of memory bits
100
together so that memory bits
100
along a given digit line
106
do not share a common word line
108
, and bits
100
along a common word line
108
do not share a common digit line
106
. In the layout of
FIG. 2
, memory bits are paired to share a common contact to the digit line, which reduces the array size.
Referring to
FIG. 2
, assume that the cell capacitors have logic one levels (+Vcc/2) stored on them. The digit lines D
0
, D
1
. . . DN and D
0
*, D
1
* . . . DN* are initially equilibrated at Vcc/2 volts. All word lines WL
0
, WL
1
. . . WLM are initially at 0 volts, which turns off the memory bit transistors. To read memory bit
1
, word line WL
0
transitions to a voltage that is at least one voltage threshold V
th
above Vcc. This elevated word line voltage level is referred to as Vccp or Vpp. When the word line voltage exceeds one V
th
above the digit line voltage (Vcc/2 in this example) and the memory bit transistor turns on, the memory bit capacitor will begin to discharge onto the digit line. Essentially, reading or accessing a DRAM cell results in charge sharing between the memory bit capacitor and the digit line capacitance. This sharing of charge causes the digit line voltage to either increase for a stored logic one or decrease for a stored logic zero. A differential voltage (Vsignal) develops between the two digit lines. The magnitude of this signal voltage Vsignal is a function of the memory bit capacitance (Cmemory_bit), digit line capacitance (Cdigit), the memory bit's stored voltage prior to the access (Vcell), and any noise terms Vnoise. For a design in which Vcell=1.65 V, Cmemory_bit=40 fF, Cdigit=300 fF and Vnoise=0, this yields a digit line change of Vsignal=194 mV.
FIG. 3
provides a graph
300
with waveforms for the cell access operation just described.
After the cell access is complete, a sensing operation can commence. The reason for forming a digit line pair will now become apparent.
FIG. 4
contains a schematic diagram for a simplified typical sense amplifier circuit
400
. Circuit
400
consists of a cross-coupled NMOS transistor pair
402
forming an N-sense amplifier, and a cross-coupled PMOS transistor pair
404
forming a P-sense amplifier. The N-sense-amp common node is labeled NLAT* (for N-sense-amp LATch). Similarly, the P-sense-amp common node is labeled ACT (for ACTive pull-up). As shown in
FIG. 5
, NLAT* is biased to Vcc/2 volts and ACT is biased to Vss or ground. Since the digit line pair D
0
and D
0
* are both initially at Vcc/2 volts, the N-sense-amp transistors are initially off due to zero Vgs potential. Similarly, both P-sense-amp transistors are initially off due to their positive Vgs potential. As discussed in the preceding paragraph, a signal voltage develops between the digit line pair DO and DO* when the memory bit access occurs. While one digit line (D
0
) contains charge from the cell access, the other digit line (D
0
*) serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp fires first and the P-sense-amp fires second. The N-sense amplifier is generally a better amplifier than the P-sense-amp because of the higher drive of NMOS transistors, and better V
th
matching. This provides for better sensing characteristics and lower probability of errors. Dropping the NLAT* signal toward ground will fire the N-sense-amp. As the voltage between NLAT* and the digit line approaches V
th
, the N-sense-amp transistor whose gate connection is to the higher voltage digit line will begin to conduct first. This conduction results in the discharge of the low voltage digit line toward the NLAT* voltage. Ultimately, the NLAT* voltage will reach ground, bringing the low voltage digit line with it. The other NMOS transistor of the N-sense-amp will not conduct since its gate voltage derives from the low voltage digit line, which is being discharged toward ground.
Shortly after the N-sense-amp fires, ACT will be driven toward Vcc volts. This activates the P-sense-amp that operates in a complementary fashion to the N-sense-amp. With the low voltage digit line approaching ground, a strong signal will exist to drive the appropriate PMOS transistor into conduction. This will charge the high voltage digit line toward ACT, ultimately reaching Vcc. Since the memory bit transistor
102
remains on during sensing, the memory bit capacitor
104
is charged to the NLAT* voltage level (for a stored logic zero) or the ACT voltage level (for a stored logic one). Thus, the voltage, and hence the charge, which the memory bit capacitor held prior to accessing will be restored to a full level. In other words, capacitor
104
will be charged to Vcc for logic one and ground for logic zero. This restoration of the charge on capacitor
104
can be referred to as a refresh operation.
For a memory write operation, the paired digit lines are charged to represent the data to be written into the memory cell. Referring back to
FIG. 1
, the word line
108
is activated to turn on the memory bit transistor
102
to connect the digit line
106
to the memory cell capacitor
104
, thereby allowing write data on D
0
/D
0
* to charge the cell capacitor. It will be appreciated that the memory read/write operations have been described herein in a simplified manner and that such access operations include numerous additional steps known to those skilled in the art.
As illustrated by
FIG. 5
, when the memory bit being accessed stores a logic one, the low voltage digit line D
0
* will be discharged toward the NLAT* voltage during a sensing operation. Similarly, when the memory bit being accessed sto

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