Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-08-31
2003-04-22
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S149000, C365S204000
Reexamination Certificate
active
06552943
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit memory devices. More particularly, the present invention relates to a sense amplifier design for integrated circuit dynamic random access memory (“DRAM”) devices (as well as those incorporating embedded DRAM) which provides improved read and write speed without requiring the use of an extra signal line which must be driven to a relatively high (or “pumped”) supply voltage level.
DRAM memory devices incorporate one or more arrays of memory cells, each generally consisting of a single transistor and associated capacitor. The transistor has one terminal coupled to an associated bit line and its gate coupled to a word line. Another terminal is generally coupled to a reference voltage level (VSS or circuit ground) through the capacitor and by enabling the transistor via the word line, the charge on the capacitor may be placed on the associated bit line. Due to the dynamic nature of the charge stored in the capacitor, it must be periodically refreshed to replenish the leaked charge.
The changes in the bit line potential due to the charge in the capacitor are first amplified by a sense amplifier to be read as either a logic level “one” or “zero” depending on the charge which has been transferred to the bit lines. Generally the sense amplifiers compare the data from the memory cells with a reference level which is stored in corresponding reference cells. At this point, the data which has been read out is then re-written to the memory cells during a precharge operation and the data is passed by means of an internal input/output (“I/O”) bus and a data amplifier to circuitry external to the memory device.
In conventional sense amplifier designs, the complementary latch nodes are either directly connected to the associated bit lines or a transistor is used to couple the latch nodes to the corresponding bit lines pair. In the latter instance, the gate of the transistor has been controlled by a signal which varied in voltage level during the operation of the sense amplifier.
SUMMARY OF THE INVENTION
Disclosed herein is a sense amplifier design for DRAM devices (as well as those incorporating embedded DRAM) which provides improved read and write speed without requiring the use of an extra signal line to the gate of a transistor coupling the sense amplifier latch nodes to the associated bit lines. In accordance with the present invention, an additional circuit element is added between the latch nodes and the bit lines which serves as a resistive path therebetween. Functionally, this additional circuit element serves to isolate the latch nodes from the relatively large bit line capacitance during a write operation such that the latch nodes can change state more quickly.
The resistance of this circuit element is carefully chosen to balance the sense amplifier write speed with bit line recovery time. In general, a higher resistance is preferable for sense amplifier write speed but less desirable for bit line recovery time. Advantageously, this additional circuit element does not need to be controlled or “clocked” thereby eliminating the need for a signal line which is driven to a high (usually “pumped”) supply voltage level. This saves power and reduces circuit complexity.
In various embodiments of the present invention disclosed herein, this additional circuit element may be an enhancement mode metal oxide semiconductor (“MOS”) transistor with its gate tied to a high supply voltage level (i.e. VCCP approximately two times the normal supply voltage) or it may be a resistor; a depletion mode MOS transistor with its gate tied to either the normal power supply voltage (VCC) or to the source or drain connection or a complementary MOS (“CMOS”) transmission (or “pass”) gate with the gate of the P-channel transistor tied to a reference voltage level (circuit ground or VSS) and the gate of the N-channel transistor coupled to VCC. The addition of this circuit element also improves the speed of read operations due to the fact that the sense amplifier latch nodes can separate more quickly during sensing.
Particularly disclosed herein is a sense amplifier circuit for an integrated circuit memory comprising first and second complementary bit lines, first and second complementary latch nodes and first and second MOS transistors respectively coupling the first bit line to the first latch node and the second bit line to the second latch node. The first and second MOS transistors each have a control terminal thereof coupled to a constant voltage source. In other embodiments of the present invention, the first and second MOS transistors may be replaced by resistors, depletion mode transistors or CMOS pass gates.
Also particularly disclosed herein is a sense amplifier circuit for an integrated circuit memory comprising first and second complementary bit lines, first and second complementary latch nodes, first and second circuit elements respectively coupling the first bit line to the first latch node and the second bit line to the second latch node and a sense amplifier coupled between the first and second latch nodes, the latch circuit comprising first and second cross coupled inverters responsive to first and second complementary latch signals.
REFERENCES:
patent: 4804871 (1989-02-01), Walters, Jr.
patent: 5267197 (1993-11-01), McClure
patent: 5936897 (1999-08-01), Koga
patent: 6147925 (2000-11-01), Tomishima et al.
patent: 6208574 (2001-03-01), Hardee
patent: 290404 (1990-10-01), None
Dense Sense Amplifier/Latch Combination, “IBM Technical Disclosure Bulletin”, Oct. 1986, vol. 29, No. 5, pp 2160-2160.*
Sense Amplifier for Capacitive Storage, “IBM Technical Disclosure Bulletin”, Jul. 1976, vol. 19, No. 2, pp 407-408.*
Memory Sense Amplifier, “IBM Technical Disclosure Bulletin”, Apr. 1976, vol. 18, No. 11 pp 3601-3603.
Ho Hoai
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
United Memories Inc.
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