Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1988-07-15
1991-04-30
Gossage, Glenn
Static information storage and retrieval
Read/write circuit
Differential sensing
365169, 365104, 365210, 365184, 307530, G11C 1718
Patent
active
050124480
ABSTRACT:
A multilevel sense circuit includes a memory MOSFET having one of at least two different current carrying states and a pair of reference MOSFETs one of which has one of the two current carrying states and the other of which has the other current carrying state. A first current supplying circuit is connected to the memory MOSFET for supplying a predetermined amount of current thereto when the memory MOSFET is activated. A second current supplying circuit is connected to the pair of reference MOSFETs and also to the first current supplying circuit, such that twice the aforementioned predetermined amount of current is supplied to the pair of reference MOSFETs when the memory MOSFET is activated. A multilevel semiconductor memory device includes a MOSFET having a channel whose width is varyingly set by providing a non-inverting region in a selected area of the channel by ion implantation.
REFERENCES:
patent: 4287570 (1981-09-01), Stark
patent: 4376987 (1983-03-01), Hsia
patent: 4388702 (1983-06-01), Sheppard
patent: 4488065 (1984-12-01), Doty, II
patent: 4604732 (1986-08-01), van Tran
patent: 4751682 (1988-06-01), Matsuoka et al.
Donoghue et al., "A 256K HCMOS ROM Using A Four-State Cell Approach", IEEE Jour. of Sol. St. Cets., vol. SC-20, No. 2, Apr. 1985, pp. 598-602.
Kosaka Daisuke
Matsuoka Shigeki
Okubo Hiizu
Gossage Glenn
Ricoh & Company, Ltd.
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