Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2003-03-19
2004-05-18
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S205000, C365S210130, C365S233100
Reexamination Certificate
active
06738296
ABSTRACT:
RELATED APPLICATION
This application claims priority from Korean Patent Application No. 2002-24484 filed on May 3, 2002 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly, to sense amplifier control circuits for memory devices.
Power supply voltages for semiconductor memory devices for use in portable systems have been increasingly lowered. However, it generally is not easy to increase the operating speed of semiconductor memory devices in such systems because of the reduced power supply voltage.
As the minimum design rule for manufacturing semiconductors has decreased, characteristics of transistors having minimum dimensions are generally more vulnerable to process variations. Delay times of internal circuits may vary with process variations and, thus, characteristics of the semiconductor devices, particularly operating speed, may deteriorate.
In a typical conventional semiconductor memory device, a bit line sense amplifier is driven by an enable signal that is generated from a sense amplifier enable signal generating circuit. The sense amplifier enable signal generating circuit typically receives an external clock signal applied from an external source and generates a sense amplifier enable signal. To perform a sensing operation after an address is applied from an external source, data stored in a memory cell (a bit cell) drives a pair of bit lines up to a predetermined level. The sense amplifier enable signal is activated. The sense amplifier enable signal generating circuit typically is configured so as to receive the external clock signal and then activate the sense amplifier enable signal after a delay of a predetermined period of time.
However, if the sense amplifier enable signal is prematurely activated (for example, when data is not fully developed on the bit lines) or delayed because of process variations, the sensing operation of the sense amplifier may be unstable or sensing speed may be reduced. Consequently, a pulse width of a word line signal for driving a pass transistor of a memory cell may have to be increased. However, this may increase power consumption. Thus, to prevent these problems from appearing in the semiconductor memory device, it is desirable that an instant when the sense amplifier enable signal is activated substantially coincides with the instant when data is fully developed to the bit lines up to a predetermined level over a range of process variations.
Conventional sense amplifier enable signal generating circuits often use an inverter delay chain or a replica technique. In a sense amplifier enable signal generating circuit that uses an inverter delay chain, a delay characteristic of the inverter delay chain and delay characteristics of a bit cell and a bit line may considerably vary with process variations. Thus, sense amplifier enable signal generating circuits that use a replica method are typically preferred.
FIG. 1
is a block diagram of a semiconductor memory device having a conventional sense amplifier enable signal generating circuit that uses a replica technique. Referring to
FIG. 1
, a sense amplifier enable signal generating circuit
100
using a replica technique includes a dummy discharge circuit
11
, a dummy bit cell block
12
, and a control circuit
13
. A path for sensing data includes a part of a decoder
18
, a word line WL, and a normal bit cell block
14
. A path for generating a sense amplifier enable signal SAEN includes a part of the decoder
18
, the dummy discharge circuit
11
, a dummy bit cell block
12
, and the control circuit
13
.
The dummy bit cell block
12
is included in the same memory array block
200
as the bit cell block
14
and is designed so that the delay time thereof is substantially equal to the delay time of the normal bit cell block
14
. The dummy bit cell block
12
includes the word line WL and a dummy bit cell
15
that is connected to a pair of dummy bit lines DBL and DBLB, and the normal bit cell block
14
includes the word line WL and a normal bit cell
16
that is connected to a pair of bit lines BL and BLB. The word line WL is connected to an output node of the decoder
18
.
The pair of dummy bit lines DBL and DBLB are connected to the dummy discharge circuit
11
, which discharges the dummy bit lines. The pair of dummy bit lines DBL and DBLB are connected to the control circuit
13
, which generates an internal clock signal ICK from an external clock signal applied from an external source and which generates a sense amplifier enable signal SAEN in response to levels of the pair of dummy bit lines DBL and DBLB. The pair of bit lines BL and BLB are connected to a sense amplifier
17
, which senses and amplifies a voltage between the pair of bit lines BL and BLB in response to the sense amplifier enable signal SAEN.
In more detail, after an address ADD is applied from an external source, the decoder
18
decodes the address ADD to activate the word line WL. As a result, data stored in the bit cell
16
is developed on the pair of bit lines BL and BLB. In response to a signal DO output from the decoder
18
and the internal clock signal ICK, the sense amplifier enable signal generating circuit
100
activates the sense amplifier enable signal SAEN after a predetermined delay time through the dummy discharge circuit
11
, the dummy bit cell block
12
, and the control circuit
13
. The sense amplifier
17
senses and amplifies a voltage between the pair of bit lines BL and BLB in response to the activation of the sense amplifier enable signal SAEN after data stored in the bit cell
16
is developed on the pair of bit lines BL and BLB up to a predetermined level.
In order that an instant when the sense amplifier enable signal SAEN is activated substantially coincides with an instant when data is developed on the pair of bit lines BL and BLB up to a predetermined level, the replica-type sense amplifier enable signal generating circuit
100
uses the dummy bit cell block
12
, which is designed so as to have substantially the same delay time as the delay time of the normal bit cell block
14
. Delay factors of the dummy bit cell
15
and the pair of dummy bit lines DBL and DBLB in the dummy bit cell block
12
are substantially identical to delay factors of the bit cell
16
and the pair of bit lines DBL and DBLB in the normal bit cell block
14
. Thus, the replica-type sense amplifier enable signal generating circuit
100
can be more stable in the presence of process variations than a sense amplifier enable signal generating circuit using an inverter delay chain.
However, as the minimum design rule in manufacturing semiconductors has decreased, characteristics of transistors having minimum dimensions may seriously vary according to process variation. Thus, a delay characteristic of the path for sensing data may be different from a delay characteristic of the path for generating the sense amplifier enable signal SAEN. In other words, due to the process variation, delay characteristics of the dummy bit cell block
12
and the dummy discharge circuit
11
may be different from a delay characteristic of the normal bit cell block
14
. In this case, the sense amplifier enable signal SAEN may be prematurely activated, i.e., when data is not fully developed to the pair of bit lines BL and BLB, or a point of time that the sense amplifier enable signal SAEN is activated may be too delayed. As a result, the sensing operation of the sense amplifier
17
may not stably be performed or the sensing speed, i.e., the operating speed, may become slower.
If the delay characteristic of the path for sensing the data differs about 20% from the delay characteristic of the path for generating the sense amplifier enable signal SAEN, a pulse width of a signal of a word line WL for driving a pass transistor in the bit cell
16
typically may have to be increased to secure stability. However, this can lead to increased power consumpt
Choi Hyun-su
Sung Nak-woo
Hoang Huan
Myers Bigel & Sibley & Sajovec
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