Sense amplifier decoding in a memory device to reduce power cons

Details Sense amplifier decoding in a memory device to reduce power cons Sense amplifier decoding in a memory device to reduce power cons

1996-12-19

1998-12-08

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711128, 711129, 711157, 711154, G06F 1200

Patent

active

058484280

ABSTRACT:
A multiple-way cache memory system incorporating circuitry for selectively enabling the sense amplifiers in a given memory bank only when the memory bank contains data that is being accessed. In the disclosed embodiment of the invention, each bank of memory incorporates a bank of at least one sense amplifier that is enabled by a separate sense amplifier control signal. The sense amplifiers in each memory bank are controlled independent of the address decoding logic. Instead, the sense amplifier control signal for each memory bank is generated from tag RAM read hit information and read address data. Preferably, no more than one bank of sense amplifiers is enabled at a time, Power consumption in the cache memory system is thereby greatly reduced.

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