Sense amplifier control circuit of semiconductor memory device

Details Sense amplifier control circuit of semiconductor memory device Sense amplifier control circuit of semiconductor memory device

2001-12-27

2002-12-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S226000

Reexamination Certificate

active

06496435

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-000475, filed Jan. 5, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND
1. Field of the Invention
Some conventional semiconductor memory devices use a sense amplifier consisting of a latch type differential amplifier circuit. The circuit arrangement of a conventional differential amplifier will be described below in terms of a sense amplifier section for amplifying the bit-line potential in a dynamic random access memory (DRAM) as an example.
2. Description of the Related Art
The sense amplifier section shown in
FIG. 1
includes a bit line pair /BL<
2
> and BL<
2
> (<
2
> is illustrated by example), an equalizer and multiplexer (EQL&MUX)
101
, an N-channel sense amplifier (NSA)
102
, an NSA common source line
103
, an NSA set driver
104
, and a DQ gate
105
. The equalizer comprises N-channel transistors (hereinafter referred to as NFETs) Q
11
, Q
12
, and Q
13
. The multiplexer comprises NFETs Q
14
and Q
15
. The NSA
102
comprises NFETs Q
16
and Q
17
. The NSA common source line
103
provides a “0” write potential VBLL (e.g., Vss) to the common sources of the NFETs Q
16
and Q
17
in the NSA
102
. The NSA set driver
104
provides VBLL to the NSA common source line
103
. The DQ gate
105
comprises NFETs Q
18
and Q
19
.
To the right of the DQ gate
105
are further provided a P-channel sense amplifier (PSA)
106
, a PSA common source line
107
, and a PSA set driver
108
. The PSA
106
comprises P-channel transistors (hereinafter referred to as PFETs) Q
20
and Q
21
. The PSA common source line
107
transfers a “1” write potential (e.g., VBLH) to the common sources of the transistors Q
20
and Q
21
in the PSA
106
, and the PSA set driver
108
provides VBLH to the PSA common source line
107
. Furthermore, the PSA
106
is followed by a multiplexer comprised of NFETs Q
22
and Q
23
and an equalizer comprised of NFETs Q
24
, Q
25
and Q
26
.
Such a sense amplifier as described above is provided for each bit line pair; thus, as shown in the lower portion of
FIG. 1
, the same circuit is also provided for /BL<
0
> and BL<
0
> (<
0
> is merely exemplary). The VBLH/
2
power supply lines on the right and left supply the equalized potential VBLH/
2
to the bit line pairs. CSL denotes a column select signal line. Though not shown, memory cells, each consisting of a cell capacitor and a cell transistor, are connected on the opposite sides of the sense amplifier section to each bit line pair.
The major part of the sense amplifier of
FIG. 1
is formed from the NSA
102
and PSA
106
each of which has its transistors cross-coupled to the bit line pair. The common source line
103
of the NSA
102
is connected by the NSA set driver
104
consisting of an NFET to a bit line restore power supply line at the “0” write potential VBLL (e.g., Vss). The common source line
107
of the PSA
106
is connected by the PSA set driver
108
consisting of a PFET to a bit line restore power supply line at the “1” write potential VBLH.
With the conventional sense amplifier, as described above, the NSA set driver is formed of an NFET and the PSA set driver is formed of a PFET. At sense time, latch signals NSET and bPSET are set high and low, respectively, thereby amplifying a small potential difference between the bit lines to set the bit line BL (or the /BL) at “1” write potential on the high potential side and the bit line /BL (or the BL) at “0” write potential on the low potential side, respectively.
SUMMARY
According to an aspect of the present invention there is provided a sense amplifier control circuit for use in a semiconductor memory device comprising: a sense amplifier comprising first transistors of a first conductivity type connected in the form of a latch type differential amplifier; a set driver corresponding to the sense amplifier; and the set driver comprising a second transistor of a second conductivity type for connecting the common source line of the latch type differential amplifier to a restore power supply line.


REFERENCES:
patent: 4855628 (1989-08-01), Jun
patent: 4948993 (1990-08-01), Chin et al.
patent: 5030859 (1991-07-01), Ihara
patent: 5130580 (1992-07-01), Min et al.
patent: 5636158 (1997-06-01), Kato et al.
patent: 6272061 (2001-08-01), Kato et al.
Yohji Watanabe et al., “A 286 mm2DRAM with × 32 Both-Ends DQ”, IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp. 567-574.

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