Sense amplifier configuration for a 1T/1C ferroelectric memory

Static information storage and retrieval – Systems using particular element – Ferroelectric

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365149, 365205, 365202, G11C 1122

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active

059699809

ABSTRACT:
A sense amplifier cell layout for use in a 1T/1C ferroelectric memory array includes a first sense amplifier having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal and a second sense amplifier having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal, wherein the combined width of the first and second sense amplifiers is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

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