Sense amplifier circuit of semiconductor memory device

Details Sense amplifier circuit of semiconductor memory device Sense amplifier circuit of semiconductor memory device

2001-11-27

2002-11-12

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000

Reexamination Certificate

active

06480037

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sense amplifier circuit of a semiconductor memory device, and more particularly to a CMOS cross-coupled sense amplifier circuit that detects and amplifies data of a memory cell.
2. Description of the Related Art
Due to technological trends in the field of semiconductors including, increased density, tighter design rules and lower supply voltages to drive memory devices, a sense amplifier that can detect and amplify voltage of memory cells has been developed to perform high speed operations but with low power consumption. A representative structure of a sense amplifier that performs high-speed operations but consumes low power is a cross-coupled device. Cross-coupled sense amplifiers have been successfully utilized to detect and amplify the voltage of memory cells in a static RAM (SRAM). The structure of such a CMOS cross-coupled sense amplifier is illustrated in FIG.
1
.
FIG. 1
is an illustration of a prior art CMOS cross-coupled sense amplifier.
FIG. 2
is a graph showing currents between drain and source (Ids) according to voltage between drain and source (Vds) and voltage between gate and source (Vgs) in a conventional N-type MOS transistor. Plots shown with a solid line and a dotted line designate the current Ids for a drain and source, respectively, in a transistor whose threshold voltage mismatches are indicated as −&Dgr;V and +&Dgr;V, respectively.
Now, operations of the prior art CMOS cross-coupled sense amplifier circuit will be briefly described with reference to
FIGS. 1 and 2
.
As shown in
FIG. 1
, the CMOS cross-coupled sense amplifier circuit includes a PMOS transistor
12
and an NMOS transistor
14
connected in a series between supply voltage Vdd and a first internal node IN
1
. The gates of PMOS transistor
12
and NMOS transistor
14
are connected to a second output node ON
2
for inverting a signal input to the gates outputting the signal to a first output node ON
1
. PMOS transistor
16
and NMOS transistor
18
are connected in series between supply voltage Vdd and a second internal node IN
2
. The gates of PMOS transistor
16
and NMOS transistor
18
are connected to a first output node ON
1
for inverting a signal input to the gates and outputting the signal to a second output node ON
2
. A first equalization transistor
20
is connected between the first and second internal nodes, IN
1
and IN
2
, for equalizing electric potential of the internal nodes, IN
1
and IN
2
in response to a control signal, CS. The control signal, CS, is input from outside at a pre-charged level. A first input transistor
22
is connected between a pull-down node PN and the first internal node IN
1
for inputting voltage of a bit line BL to a gate. A second input transistor is connected between the pull-down node PN and the second internal node IN
2
for inputting voltage of a bit line BLB to its gate. A driving transistor
26
is connected between the pull-down node PN and ground for pulling down the electric potential of the pull-down node PN to a ground level in response to a control signal, CS, input to its gate is at a driving level. BLB is the complement bit line of bit line BL.
Reference numerals
28
and
30
are pre-charge transistors connected between supply voltage Vdd and the first output node ON
1
, and between supply voltage Vdd and the second output node ON
2
, respectively. The pre-charge transistors
28
and
30
pre-charge the first and second output nodes ON
1
and ON
2
to the level of supply voltage, Vdd, by switching when the control signal, CS, input to gates of the transistors is at the pre-charge level. In addition, reference numeral
32
is a second equalization transistor. The second equalization transistor
32
equalizes the electric potential of the two output nodes ON
1
and ON
2
, in response to an input of a pre-charged level of a control signal CS. As shown in
FIG. 1
, the first and second input transistors
22
and
24
, and the driving transistor
26
are NMOS transistors. The first and second equalization transistors
20
and
32
, and pre-charge transistors
28
and
30
are PMOS transistors.
Operations of the CMOS cross-coupled sense amplifier circuit thus constructed will be described briefly. A control signal, CS, to drive the sense amplifier, maintains an initial low level of logic but turns into a “high” level of logic for a predetermined period of time when a semiconductor memory device is activated. For example, when a low address strobe signal is activated to allow data input and output to memory cells (not shown). Accordingly, if the control signal, CS, is low and input at the pre-charge level, the pre-charge transistors
28
and
30
, and the first and second equalization transistors,
20
and
26
, are all “turned on”. At the pre-charge mode as such, the first and second output nodes, ON
1
and ON
2
, are pre-charged to the level of supply voltage, “Vdd”, and, equalized by the second equalization transistor to get ready to detect and amplify the electric potential of bit lines BL/BLB. The electric potential of the first and second internal nodes, IN
1
and IN
2
, is equalized by turning on the first equalization transistor
20
. After completion of pre-charge and equalization operations, bit lines, BL and BLB, are to be maintained at the same electric potential.
After a memory cell (not shown) is selected to develop its electric potential, it is transferred to bit lines BL and BLB, connected to the related memory cell and provided to the NMOS transistors
22
and
24
. At this time, when the control signal, CS, is activated to its high level from its low level of logic, the sense amplifier, shown in
FIG. 1
, is driven. The pre-charge transistors
28
and
30
, and the first and second equalization transistors,
20
and
32
, are turned off, and the driving transistor
26
is turned on to pull down the electric potential of the pull-down node PN to ground. If the driving transistor
26
is turned on, the sense amplifier circuit, shown in
FIG. 1
, amplifies a voltage difference developed in the electric potential from the memory cell and outputs it to the first and second output nodes, ON
1
and ON
2
.
For example, if a voltage offset loaded at bit lines BL and BLB, exceeds a predetermined level of voltage, e.g., if the voltage offset of the bit lines BL and BLB develop into (+)/(−), the voltage of the first and second internal nodes, IN
1
and IN
2
, increases in different directions by operations of the first and second input transistors,
22
and
24
. The voltage of the first and second internal nodes, IN
1
and IN
2
, is amplified by the four transistors
12
,
13
,
14
and
16
, connected in the latch type between the first and second internal nodes, IN
1
and IN
2
, and then, output to the first and second output nodes, ON
1
and ON
2
, as levels of logic, “low, high” or “high, low”.
The conventional sense amplifier circuit shown in
FIG. 1
performs its normal operations if the voltage offset of bit lines BL and BLB become greater than a predetermined level, but does not perform its normal operations if the voltage offset of bit lines BL and BLB becomes smaller than a predetermined level. A minimum voltage offset of the bit lines BL and BLB that can operate the sense amplifier circuit is defined as a voltage margin of a sense amplifier. As the minimum voltage offset as such becomes smaller, the sense margin of a sense amplifier is considered favorable. As the minimum voltage offset becomes greater, the sense margin of a sense amplifier is considered poor.
However, the sense amplifier shown in
FIG. 1
has a large number of inter-related transistors, so it may not operate with an input level of voltage offset because of a mismatch among transistors. The mismatch includes a mismatch in the thickness or length of channels, in capacitance or in threshold voltage, thereby transistors behave differently with variations in the manufacturing process. In other words, a sense amplifier may have a worse sense marg

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