Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
1999-12-16
2001-05-15
Mai, Son (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S205000, C365S210130
Reexamination Certificate
active
06233170
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sense amplifier circuit, a memory device using the circuit, and a method for reading the memory device. More specifically, the present invention relates to a method for reading a ferroelectric memory device made of a ferroelectric material.
2. Description of the Related Art
Conventionally, a ferroelectric capacitance has a hysteresis between an applied voltage and polarization. Therefore, a ferroelectric memory device can sustain data by remaining polarization even if the applied voltage becomes zero after writing data by applying a voltage to the ferroelectric capacitance. This characteristic is used for making up a nonvolatile ferroelectric memory device.
When reading data out of the nonvolatile ferroelectric memory device, a sense amplifier having a differential voltage input determines the state 0 or 1 of data memorized in the memory cell. Therefore, it is necessary to generate a voltage corresponding to the data 0 or 1 on the bit line before determining the state 0 or 1 by the sense amplifier. The bit line voltage corresponding to the voltage memorizing data can be realized by applying a voltage to the ferroelectric to read polarization charge onto the bit line.
A method for applying a voltage to such a ferroelectric is disclosed in Japanese Patent No. 2674775, U.S. Pat. No. 5,530,668, or Japanese Patent Publication Hei 8-8339.
The first prior art method disclosed in the Japanese Patent No. 2674775 will be explained with reference to
FIGS. 1
to
3
. In
FIGS. 1 and 2
, the bit lines BLa
1
and BLa
2
are precharged by a bit line precharge signal PBL to the ground level, and the plate line PLa
1
is at the ground level.
The memory cell MCa
1
is selected when the word line WLa
1
becomes the high level. When the plate line PLa
1
is driven to VCC, a voltage is applied to the ferroelectric CFa
1
, and the polarization charge is read out on the bit line BLa
1
. Since the bit line BLa
1
has a parasitic capacitance, a bit line voltage is generated in accordance with polarization charge corresponding to the data 0 or 1 sustained in the memory cell MCa
1
.
FIG. 3
shows the bit line voltage when the polarization charge sustained by the memory cell MCa
1
is read out on the bit line BLa
1
. The bit line voltage depends on the relationship between the hysteresis characteristic of the ferroelectric CFa
1
and the bit line capacitance. The bit line voltage becomes V
1
upon reading when the polarization of the ferroelectric CFa
1
switches, while it becomes V
0
when the polarization does not switch.
The sense amplifier SAa
1
determines the state 0 or 1 of the read data by the dummy cell DMCa
1
using a reference voltage generated on the other bit line BLa
2
. After that, for rewriting, the plate line PLa
1
is connected to the ground potential, the sense amplifier SAa
1
is changed to non-active state, the bit lines BLa
1
and BLa
2
are discharged to the ground level, and the word line WLa
1
is connected to the ground potential so as to finish the read or write cycle.
The second prior art method disclosed in the U.S. Pat. No. 5,530,668 will be explained with reference to
FIGS. 1 and 4
. In these figures, the bit lines BLa
1
and BLa
2
are precharged by the bit line precharge signal PBL to 5 volts, and the plate line PLa
1
is connected to the ground potential.
The memory cell MCa
1
is selected when the word line WLa
1
becomes the high potential level. Since the bit line BLa
1
is precharged to 5 volts, when the word line WLa
1
becomes high level and the cell transistor TCa
1
becomes conduction, a voltage is applied to the ferroelectric CFa
1
without driving the plate line PLa
1
, and the bit line voltage is generated. After that, the sense amplifier SAa
1
determines 0 or 1 state. In addition, the plate line PLa
1
is driven for rewriting. The plate line PLa
1
is driven only for rewriting, so that an access speed can be improved.
Furthermore, the third prior art method disclosed in Japanese Patent Publication Hei 8-8339 will be explained with reference to FIG.
5
. In this figure, the plate line PLa
1
is fixed to the potential VCC/2. In addition, the bit lines BLa
1
and BLa
2
are precharged to VCC/2 during waiting period, and precharged to the ground level or VCC before the memory cell MCa
1
is selected. Therefore, when the word line WLa
1
selects the memory cell MCa
1
and the cell transistor TCa
1
becomes conduction, a voltage is applied to the ferroelectric FCa
1
without driving the plate line PLa
1
, so that the bit line voltage is generated.
After that, the sense amplifier SAa
1
determines the 0 or 1 state and performs rewriting. Since the voltage of the plate line PLa
1
is VCC/2, the rewriting is finished without driving the plate line PLa
1
. In addition, since a potential of a cell node NCa
1
is sustained at VCC/2 during the waiting period, all word lines are set to the high levels so that the potential of the cell node NCa
1
is secured. Thus, refreshing operation is not required.
In
FIG. 1
, DPLa
1
denotes a dummy plate line, DFCa
1
denotes a dummy ferroelectric, DTCa
1
denotes a dummy cell transistor, and DNCa
1
denotes a dummy cell node.
The conventional nonvolatile ferroelectric memory device explained above has a problem in the method for applying a voltage to the ferroelectric. Namely, in the first prior art method where the plate line is driven, the access time is lengthened. This problem is caused by a large time constant of the plate line that makes the driving time long for obtaining a sufficient level of the signal voltage.
In addition, in the second prior art method where the plate line is not driven, power consumption during waiting period increases. This problem is caused by that a leak current should be compensated for securing the bit line voltage at 5 volts during waiting period.
Furthermore, in the third prior art method where the plate line is not driven, the control becomes complicated, the power consumption increases and the access time is lengthened. In the third method, the potential of the plate line is fixed to VCC/2, the refreshing operation is not required. Therefore, the bit line potential during waiting period is set to VCC/2 that is the same as the plate line potential, and all word lines are set to the high level so as to make the cell transistor conduction.
However, just before memory access operation, it is necessary to set all word lines to the ground potential and to precharge the bit line to the ground potential or VCC, so as to reset only the selected word line to the high level. Therefore, the control of the word line and the control of the bit line precharge become complicated. In addition, the access time is lengthened and power consumption is increased since the word line and the bit line are driven many times.
SUMMARY OF THE INVENTION
In order to an solve the above-mentioned problems, an object of the present invention is to provide a sense amplifier circuit that can realize reading and writing operation by a simple control and can substantially improve the operation speed as well as the power consumption, a memory device using the circuit and a method for reading the memory device.
A sense amplifier circuit according to the present invention is connected to two bit lines of a memory cell array including a plurality of memory cells disposed in rows and columns for memorizing information, a plurality of bit lines disposed corresponding to the columns of the plurality of memory cells, and a plate line connected to the plurality of memory cells. The sense amplifier circuit is activated in the state where the plate line is not driven and the potential levels of the plate line and the bit lines are identical to each other upon reading.
A memory device according to the present invention comprises a memory cell array including a plurality of memory cells disposed in rows and columns for memorizing information, a plurality of bit lines disposed corresponding to the columns of the plurality of memory cells, and a plate line
Mai Son
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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