Sense amplifier circuit having high speed operation

Details Sense amplifier circuit having high speed operation Sense amplifier circuit having high speed operation

1997-07-22

1999-12-07

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Differential sensing

365202, 365208, G11C 700

Patent

active

059994703

ABSTRACT:
A sense amplifier circuit is disclosed which has an amplifier circuit stage 11 outputting a intermediately signal S and SB having a first level voltage which makes a driver circuit M7 and M8 of the output circuit stage 12 into turn off when the sense amplifier circuit SA1 is in a inactive state. As a result, circuits which bring the driver circuit to a high impedance state can be unnecessitated. Accordingly, load capacities added to the output nodes A and B of the amplifier circuit stage 11 can be reduced to realize an operation of high speed, and markedly reduce the number of circuit elements.

REFERENCES:
patent: 4910713 (1990-03-01), Maddem et al.
patent: 4922461 (1990-05-01), Hayakawa et al.
patent: 5325335 (1994-06-01), Ang et al.
patent: 5650971 (1997-07-01), Longway et al.
patent: 5687127 (1997-11-01), Takahashi
patent: 5708607 (1998-01-01), Lee et al.
Teruo Seki, et al. "A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier", IEEE Journal of Solid-State Circuits, vol. 28, No. 4, Apr. 1993, pp. 478-482.

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