Sense amplifier circuit for large-capacity semiconductor memory

Details Sense amplifier circuit for large-capacity semiconductor memory Sense amplifier circuit for large-capacity semiconductor memory

1990-01-03

1991-09-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

For complementary information

365205, 307530, G11C 1140

Patent

active

050519573

ABSTRACT:
A sense amplifier circuit for a semiconductor memory includes a flip-flop coupled to a pair of bit lines connected to memory cells, for amplifying a differential read voltage produced between the bit lines, and at least two switches for applying respectively different levels of drive voltage to a common node of the flip-flop. The switches are controlled such as to apply a relatively high value of drive voltage to the common node when a read operation is initiated, to thereby initially provide a high charging current to the bit line capacitance, and thereafter supply a lower value of drive voltage to thereby ensure reliability of the memory cell oxide film.

REFERENCES:
patent: 4751682 (1988-06-01), Matsuoka et al.
Dhong et al., "A High Performance Sensing Scheme for CMOS Drams," IBM Technical Publication, vol. 6-5, pp. 83-84.
Okamura et al., "Decoded-Source Sense Amplifier for High-Density DRAMs," Publication of Toshiba Corporation, pp. 103-104.
Kimura et al., "A 65-ns 4-MBit CMOS DRAM with a Twisted Driveline Sense Amplifier," IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 651-656.

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