Sense amplifier circuit and semiconductor storage device

Details Sense amplifier circuit and semiconductor storage device Sense amplifier circuit and semiconductor storage device

2000-09-13

2001-10-09

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S206000, C365S202000, C365S205000, C365S191000

Reexamination Certificate

active

06301180

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the semiconductor storage devices, and more particularly to latch-type sense amplifier circuits that may be used in semiconductor storage devices.
BACKGROUND OF THE INVENTION
Many conventional semiconductor storage devices typically contain a number of memory cells that can generate some sort of data signal when accessed. For example, a memory cell may generate a particular current and/or voltage differential. Due the desirability of high density semiconductor storage devices, memory cells are typically manufactured to be as small as possible. Consequently, the data signal generated by a memory cell can be correspondingly small. Therefore, an important aspect of many semiconductor storage devices can be the speed at which such small memory cell signals can be amplified and thus “sensed.” Typically, an amplifier used to detect a memory cell signal is referred to as a sense amplifier (or sense amp).
While various types of semiconductor storage devices include memory cells and sense amplifiers, one particular semiconductor storage device is currently being used in an increasing number of applications. Nonvolatile storage devices, which can include electrically erasable programmable read only memories (EEPROMs), are becoming increasingly popular due to their ability to retain data in the absence of power. Such a capability can be a valuable feature in portable electronic devices that may run off batteries.
To assist in understanding the various capabilities, features and advantages of the present invention, a conventional EEPROM and its sensing operation will now be described.
Referring now to
FIG. 9
, a conventional EEPROM is shown in a block schematic diagram. A conventional EEPROM may include a memory cell array
020
having a number of memory cells arranged into rows and columns. Memory cells are indicated by the character (MC
km
), where k may vary from 0-i, and indicate a column, while m may vary from 0-n, and indicate a row.
In the example of
FIG. 9
, each memory cell may include a transistor with a floating gate. The threshold voltage of such transistors may be affected by the presence or absence of charge on their respective floating gates. In particular, a memory cell transistor may have essentially no charge on its floating gate (be in an initial condition) and therefore have an initial state threshold voltage. In addition, a memory cell transistor may have some charge, due to the addition of electrons to the floating gate (be in a programmed condition). Thus, the threshold voltage in an initial condition can be different from that of a programmed condition.
In one arrangement, memory cell transistors in an initial condition can store a value “1” while memory cell transistors in a programmed condition can store a value “0.” In a read operation, a voltage can be applied t o a control gate of a memory cell. According to the condition of the memory cell (e.g., initial or programmed condition) a particular current will flow through the memory cell. As but one example, a memory cell may include an n-channel field effect transistor with a floating gate, in which case a programmed condition will have a higher threshold voltage than an initial condition. Accordingly, in response to a voltage at its gate, a memory cell in an initial state may draw less current than a memory cell in a programmed state. In some conventions a memory cell in an initial state can be referred to as an “on” memory cell while a memory cell in a programmed state can be referred to as a “off” memory cell.
In many configurations, a number of memory cells can be connected to a digit line. In a read operation, a selected memory cell can be connected to a single digit line. Thus, a typical EEPROM arrangement will detect a current drawn on a digit line when reading data from a selected memory cell. Because EEPROM memory cells usually draw a current, an EEPROM device will often include current-to-voltage (I-V) converter circuits that can converts a memory cell current into a voltage. Such a voltage may then be compared to a reference voltage and amplified in a sense amplifier to generate a logic “1” or “0.” The operation of I-V converter circuits and associated sense amplifiers will be discussed in more detail below.
In the particular EEPROM configuration of
FIG. 9
, memory cells (MC
00
-MC
in
) of the same row may be commonly connected to a word line. Such word lines may be connected to a word line driving circuit
010
. A row decoder circuit (not shown) can decode a row address from an input signal, and provide such decoded values as inputs to a word line driving circuit
010
. In response to such inputs, a word line driving circuit
010
can drive the word lines. A driven word line can connect memory cells (MC
00
-MC
in
) to digit lines, thereby selecting the memory cells (MC
00
-MC
in
).
In
FIG. 9
, memory cell transistors may have drains connected to digit lines DIG
0
-DIG
i
in a column-wise fashion. Digit lines (DIG
0
-DIG
i
) can be selected by a column decoder (not shown) and connected to corresponding I-V converter circuits
030
0
-
030
i
in various ways. A column decoder may decode a column address to generate column select signals for selecting particular digit lines. As but one example, a column decoder may provide direct connections between digit lines (DIG
0
-DIG
i
) and I-V converter circuits (
030
0
-
030
i
). As but another of the many possible examples, digit lines may have a layered and/or hierarchical arrangement that includes main digit lines and sub-digit lines. In such an arrangement, the drains of memory cell transistors may be connected to sub-digit lines. A column switch circuit (not shown) may then connect a memory cell to a I-V converter circuit (
030
0
-
030
i
) by way of a sub-digit line and corresponding main digit line.
Referring again to
FIG. 9
, I-V converter circuits (
030
0
-
030
i
) can convert a current value, taken from the current flowing in a digit line (DIG
0
-DIG
i
) into a voltage value (SAVD
0
-SAVD
i
). Such a voltage value can then be supplied to sense amplifier circuits (
050
0
-
050
i
).
An EEPROM according to
FIG. 9
may further include a reference cell
021
and corresponding I-V converter circuit, also referred to as a reference voltage generating circuit
040
. In one particular arrangement, a reference cell
021
may include an on (initial condition) cell, shown as “ON Cell” and an off (programmed condition) cell, shown as “OFF Cell.” An on cell current can be drawn in a digit line DIGRON connected to the ON Cell. An off cell current can be drawn on a digit line DIGROFF connected to the OFF Cell.
A reference voltage generating circuit
040
can receive current values from the DIGRON and DIGROFF lines as inputs. In response to such inputs, a reference voltage generating circuit
040
may generate a reference voltage VREF that can be halfway between a voltage generated in response to the DIGRON current and a voltage generated in response to a DIGROFF current.
As shown in
FIG. 9
, each sense amplifier circuit (
050
0
-
050
i
) may include a first input SA
1
and second input SA
2
. A first input SA
1
may receive an input voltage SAVD
0
-SAVD
i
from a corresponding I-V converter circuit (
030
0
-
030
i
). The second inputs SA
2
can receive a reference voltage VREF from reference voltage generating circuit
040
.
Sense amplifier circuits (
050
0
-
050
i
) may further receive a sense amplifier latch activating signal BSAL. In response to the sense amplifier latch activating signal BSAL, each sense amplifier circuit (
050
0
-
050
i
) can latch and amplify a voltage difference between its inputs SA
1
and SA
2
. Such amplified voltage differences may be provided as amplifier output signals TDIO
0
-TDIO
i
.
Amplifier output signals TDIO
0
-TDIO
i
may be provided to an internal bus
060
. Amplifier output signals (TDIO
0
-TDIO
i
) on an internal bus
060
may then be provided as on output terminals as data out values DO
0
-DO
i
.
It is noted that the various sense amplifier circuits (
050
0
-
050

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