Sense amplifier circuit

Details Sense amplifier circuit Sense amplifier circuit

2007-12-04

2007-12-04

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S194000, C327S055000, C327S057000, C327S065000

Reexamination Certificate

active

11337348

ABSTRACT:
A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.

REFERENCES:
patent: 6091654 (2000-07-01), Forbes et al.
patent: 6462585 (2002-10-01), Bernstein et al.
patent: 6741104 (2004-05-01), Forbes et al.
patent: 6865129 (2005-03-01), Morishima
patent: 6954391 (2005-10-01), Baker
L. Mathew, et al., “CMOS Vertical Multiple Independent Gate Field Effect Transistors (MIGFET)”,2004 IEEE Int. SOI Conference, Oct. 2004, pp. 187-189.
T. Cakici, et al., “A Low Power Four Transistor Schmitt Trigger for Asymmetric Double Gate Fully Depleted SOI Devices”,IEEE Int. SOI Conference, 2003, pp. 21-22.
H. Mahmoodi, et al., “High-Performance and Low-Power Domino Logic Using Independent Gate Control in Double-Gate SOI MOSFETs”,2004 IEEE Int. SOI Conference, Oct. 2004, pp. 67-68.
T. Kobayashi, et al., “A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture,”IEEE J. Solid-State Circuits, vol. 28, No. 4, Apr. 1993, pp. 523-527.
B. Wicht, et al., “Yield and Speed Optimization of a Latch Type Voltage Sense Amplifier”,IEEE Journal of Solid-State Circuits, vol. 39, No. 7, Jul. 2004, pp. 1148-1158.
M. Sinha, et al., “High-Performance and Low-Voltage Sense-Amplifier Techniques for sub-90nm SRAM,”Proceedings of IEEE Int. SOC Conference, Sep. 2003, pp. 113-116.
R. Sarpeshkar, et al., “Mismatch Sensitivity of a Simultaneously Latched CMOS Sense Amplifier”,IEEE Journal of Solid-State Circuits, vol. 26, No. 10, Oct. 1991, pp. 1413-1422.
A. Kumar, et al., “Low Voltage and Performance Tunable CMOS Circuit Design Using Independently Driven Double Gate MOSFETs”,2004 IEEE Int. SOI Conference, Oct. 2004, pp. 119-121.
S. Mukhopadhyay, et al., “Design of High Performance Sense Amplifier Using Independent Gate Control in Sub-50nm Double-Gate MOSFET”, Proceedings of the Sixth Int'l Symposium on Quality Electronic Design, Mar. 2005.

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