Sense amplifier circuit

Static information storage and retrieval – Read/write circuit – Differential sensing

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Details

365203, 36518906, 36518911, G11C 700

Patent

active

053052722

ABSTRACT:
In a sense amplifier circuit, an output potential is set in a data output state when an operation of the sense amplifier is a worst pass before the start of read access. In a memory read mode, when data corresponding to the worst-pass operation of the sense amplifier circuit is read out, the circuit is previously set in a corresponding data output state. A time delay (gate delay) by a gate does not occur. In contrast, when data corresponding to the best-pass operation of the sense amplifier circuit is read out, the gate delay occurs by this operation. The gate delay, however, is shorter than that of the worst pass. As a result, only the best pass is present as the operation mode of the sense amplifier circuit. Therefore, a high operation speed is achieved, so that a high read speed of the entire memory is achieved.

REFERENCES:
patent: 4239994 (1980-12-01), Stewart
patent: 4313179 (1982-01-01), Heimeier et al.
patent: 4412143 (1983-10-01), Patella et al.
patent: 4439843 (1984-03-01), Takamatsu
patent: 4451906 (1984-05-01), Ikeda
Kayano et al., "25-ns 256 Kx1/64x4 CMOS SRAM's," I.E.E.E. Journal of Solid State Circuits SC-21 Oct. 1986, No. 5, pp. 686-691.
Flannagan et al., "Two 13-ns 64K CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques," I.E.E.E. Journal of Solid State Circuits SC-21, Oct. 1986, No. 5, pp. 692-703.

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