Sense amplifier bitline boost circuit

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S205000

Reexamination Certificate

active

10988787

ABSTRACT:
A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.

REFERENCES:
patent: 4866674 (1989-09-01), Tran
patent: 4951252 (1990-08-01), White et al.
patent: 5982666 (1999-11-01), Campardo
patent: 6469929 (2002-10-01), Kushnarenko et al.
Debrosse, J., et al., “A High-Speed 128-kb MRAM Core for Future Universal Memory Applications,” IEEE Journal of Solid-State Circuits, Apr. 2004, pp. 678-683, vol. 39, No. 4.
Tehrani, S., et al., “Recent Developments in Magnetic Tunnel Junction MRAM,” IEEE Transactions on Magnetics, Sep. 2000, pp. 2752-2757, vol. 36, No. 5.

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