Sense amplifier bit line isolation scheme

Details Sense amplifier bit line isolation scheme Sense amplifier bit line isolation scheme

1985-02-11

1987-03-17

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365210, G11C 700

Patent

active

046513051

ABSTRACT:
In a CMOS ROM memory arrangement, the use of the least significant column address bit to perform the dual function of even/odd bit line select and the disconnection of the selected bit line (17' and 17") from the sense amplifier (66) driven, in order to reduce its capacitive load, prior to the time of latching the information into the sense amplifier (66).

REFERENCES:
patent: 4169233 (1979-09-01), Haraszti
patent: 4441171 (1984-04-01), Hoffmann
patent: 4555777 (1985-11-01), Poteet

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