Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2001-04-12
2002-08-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S095000, C326S112000, C326S119000
Reexamination Certificate
active
06433589
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to digital integrated circuits, and more particularly to dynamic logic circuits implemented in Silicon-On-Insulator (SOI) technology wherein differential signals are detected.
2. Description of the Related Art
Dynamic logic circuits are frequently used in integrated circuits, particularly in very large scale integrated circuits (VLSI). Dynamic logic circuits are widely used in semiconductor memories, microprocessors and large logic arrays. Recently, Silicon-On-Insulator (SOI) technology has been used to implement dynamic circuits within semiconductor memories and microprocessors. SOI integrated circuits provide shorter delays and lower power dissipation due to reduced substrate capacitance. SOI channel material is formed within a “trench” above an oxide insulating layer, reducing resistive leakage to the substrate and capacitive loading by the substrate. The “body” of an SOI transistor is the channel material to which the source and drain complementary material is added. For an N-channel transistor, the body is generally P type material and the source and drain are both formed from N+ type material. The body is electrically isolated, in contrast to non-insulated technologies that form the channel material on a conducting substrate. In non-insulated technologies, the substrate is biased to a power supply rail, raising the capacitive loading on the transistor terminals and thus reducing the switching speed of the transistors formed in non-insulated technologies.
Sense amplifiers are used within dynamic logic circuits and most particularly within memory circuits to detect differential signals provided by “bitlines”. The bitlines are the outputs of the storage array and the access delay of the memory may be limited by the capacitance of the bitline. Thus, the speed of a memory of a given size is dependent on the speed at which the voltage differential present on the bitlines can be reliably detected. This speed limitation is also dependent on the power supply voltage within the storage array, since for reduced power supply voltage, the voltage differential is proportionately reduced at time of measurement.
Sense amplifiers implemented in SOI circuit designs use a cross-coupled amplifier structure to provide a bistable circuit having differential inputs and outputs. A differential input transistor pair is used to detect a voltage difference during an evaluation period in which the differential state of the input signals is determined, producing the correct state of the sense amplifier outputs. In SOI technology, the “body” of the transistors is insulated from the substrate, and therefore is not implicitly biased as in typical metal-oxide semiconductor (MOS) technology. If the body of the input transistors is not biased, charge accumulating on the body can cause improper operation of a sense amplifier, since the accumulated charge affects the threshold voltage of the input transistors. The charge accumulation effect can cause “history dependence” (since the charge accumulation is a function of the previous switching history of the amplifier).
Typically, the bodies of the sense amplifier input transistors are biased to a fixed reference by coupling the bodies to ground for an N-channel ground-referenced input, or coupling the bodies to the power supply rail for a P-channel rail referenced input.(mention pending app) Biasing the input transistor bodies with a fixed reference is disadvantageous in that parasitic capacitance from the gate to the body loads the input signal with the full value of the gate to body capacitance, delaying switching of the sense amplifier input transistors and thus increasing sense amplifier evaluation time.
It would therefore be desirable to eliminate the history dependence of the input transistors in a SOI sense amplifier without biasing the bodies of the input transistors with a fixed reference.
SUMMARY OF THE INVENTION
The objective of eliminating the history dependance of the input transistors in an SOI sense amplifier is accomplished in an improved sense amplifier and method for sensing signals in a silicon-on-insulator integrated circuit. The improved sense amplifier is a dynamic logic circuit fabricated on a substrate including a sense amplifier with a latch transistor that has a body insulated from the substrate and an input transistor coupled to the latch transistor. The input transistor also has a body insulated from the substrate and the body of the input transistor and the body of the latch transistor are coupled to an input of the dynamic logic circuit. The threshold voltages of both the input transistor and the latch transistor are altered by the signal on the input of the dynamic logic circuit, yielding an improved switching speed.
The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5986924 (1999-11-01), Yamada
patent: 6037808 (2000-03-01), Houston et al.
patent: 6061267 (2000-05-01), Houston
patent: 6177811 (2002-01-01), Fuse et al.
U. S. patent application Ser. No. 09/316,753.
U. S. patent application Ser. No. 09/345,720.
Harris Andrew M.
Salys Casimer
Tokar Michael
Tran Anh
Weiss & Moy P.C.
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