Sense amplifier and latching circuit for an SRAM

Details Sense amplifier and latching circuit for an SRAM Sense amplifier and latching circuit for an SRAM

1992-04-17

1994-02-22

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

For complementary information

365154, 365203, 365208, G11C 700, G11C 702, G11C 1100

Patent

active

052894150

ABSTRACT:
A memory circuit uses sense amplifiers to amplify a low level differential data signal from the memory cells to full logic levels. A first sense amplifier converts the low level differential data signal to an intermediate differential voltage level at first and second nodes during the read cycle. A second sense amplifier converts the intermediate differential voltage level to the full logic level. The first and second sense amplifiers are powered down after sensing is complete. A circuit drives the intermediate differential data signal to an equilibrium voltage level when the sensing is complete to reduce the power up delay time of the second sense amplifier and thereby increase the operating speed of the memory circuit. A latching circuit is synchronized with the power down of the first sense amplifier to latch the output logic level at the end of the read cycle.

REFERENCES:
patent: 4542483 (1985-09-01), Procyk
patent: 4750155 (1988-06-01), Hsieh
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 5007024 (1991-04-01), Tanaka et al.
patent: 5065363 (1991-11-01), Sato et al.
patent: 5126974 (1992-06-01), Sasaki et al.
patent: 5153459 (1992-10-01), Park et al.

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