Sense amplifier

Details Sense amplifier Sense amplifier

2000-09-29

2002-06-11

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S390000, C257S401000, C257S618000, C257S653000, C257S202000, C257S206000

Reexamination Certificate

active

06404019

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the design and manufacture of integrated circuit devices including memory and random access memory, and more particularly, to the design of transistors in a support area of the memory which allows support circuits, such as sense amplifiers, to be designed with a width commensurate with the width of the memory cells.
BACKGROUND OF THE INVENTION
There is a continuing trend towards increasing the capacity and speed, and decreasing the cost of dynamic random access memory (DRAM) fabricated in semiconductor integrated circuits. Such an increase in capacity and decrease in cost is best achieved by decreasing the area of the memory cells, and by decreasing the size of the support circuitry, sense amplifiers and addressing circuitry, to be commensurate with the smaller size of the memory cells.
In a typical DRAM memory cells are arranged in an array, which in most designs consumes a major portion of the area of the DRAM semiconductor integrated circuit.
FIG. 1
shows a schematic block diagram of a prior art memory
100
having individual memory cells
110
arranged in a top array
120
and a bottom array
130
. Word lines
140
run horizontally, and pairs of bit lines
150
run vertically, across the arrays
120
,
130
of memory cells
110
, and are coupled to the memory cells
110
. When one of the word lines
140
is selected, the memory cells
110
in a given row are accessed and connected to the corresponding pair of bit lines
150
. The pairs of bit lines
150
run vertically through both the top array
120
and the bottom array
130
of memory cells
110
and connect to the sense amplifiers
160
, which are typically located centrally between the two arrays
120
and
130
. The largest portion of the surface area of a memory circuit
100
is devoted to the two arrays
120
and
130
of memory cells
110
. The size of a memory circuit
100
is thus directly proportional to the size of the arrays
120
and
130
of memory cells
110
. The size of the memory cells
110
can be characterized by the horizontal pitch, or distance from cell-to-cell, of the memory cells
110
. If the size or pitch of the sense amplifiers
160
is greater than that of the memory cells
110
, the sense amplifier
160
, rather than the memory cell
110
, will be the determining factor in the size of the complete memory circuit
100
.
Various techniques have been used to decrease the size of the memory cells, including the use of exotic high dielectric constant insulator materials in the storage capacitors, the use of vertical structures for the storage capacitors and access transistors, and the use of particular shapes and layouts for the active area of the memory cell. By the use of these techniques the horizontal size of an individual memory cell
110
has been reduced to the point where it is comparable with the size of the pair of bit lines
150
. It is incumbent upon the circuit designer to be able to produce a sense amplifier
160
of equivalent width.
It is common practice to describe the size of a memory cell or sense amplifier in terms of the size of the smallest features which can be produced using the available photolithographic and pattern definition techniques. Such a minimum size feature is commonly denoted as F. The minimum pitch of the bit lines is denoted herein as P. If one assumes that the minimum width of a bit line, F, is equal to the space between the bit lines, then the pitch of a pair of bit lines will be 4F. Thus the size of the smallest memory cells described above is said to be 4F, or more generally, 2P, or less. The goal of the designers of sense amplifiers is to achieve a sense amplifier with a width of 2P, or less.
FIG. 2A
shows a schematic circuit diagram a of prior art sense amplifier
200
fabricated in Complementary Metal Oxide Semiconductor (CMOS) transistor technology. The details of the operation of the circuit depicted in
FIG. 2A
is described in the existing literature. The circuit contains three n-channel Metal Oxide Semiconductor (MOS) transistors N
1
, N
2
, and N
3
, and three p-channel MOS transistors, P
1
, P
2
, and P
3
, connected as shown in FIG.
2
A. Two of the p-channel MOS transistors, P
2
and P
3
, and two of the n-channel MOS transistors, N
2
and N
3
, are connected to form a latch circuit. The remaining p-channel MOS transistor P
1
is connected as a switch from a positive power supply
230
to sources of the two p-channel MOS latch transistors P
2
and P
3
, and the remaining n-channel MOS transistor N
1
is connected as a switch from the sources of the two n-channel MOS latch transistors N
2
and N
3
to a reference potential which is shown as ground
280
. The switch transistors P
1
and N
1
, respectively, are switched off and on by p-enable/disable and n-enable/disable signals (not shown) applied to gates
240
and
250
, respectively, of transistors P
1
and N
1
, respectively. The gates of the transistors P
2
and N
2
, and P
3
and N
3
, are connected to a Data Bit Line
260
and Reference Bit Line
270
, respectively, as is shown. While one switch transistor, P
1
or N
1
, is shown connected to a single pair of latch transistors, P
2
and P
3
or N
2
and N
3
, respectively, the circuit can alternatively be implemented with a single pair of switch transistors supplying power and ground to multiple pairs of transistors of the latch circuit. The number of pairs of transistors of the latch circuit connected to a single switch transistor (P
1
or N
1
) is a design parameter and is typically determined by the resistance of the interconnection (not shown) between the switch transistors and transistors of the latch circuit.
FIG. 2B
is a representation of the circuit of
FIG. 2A
in which the circuit has been redrawn to segregate the p-channel MOS transistors (P
1
, P
2
, and P
3
) into one p-channel region
211
(shown in dashed lines), and the n-channel MOS transistors (N
1
, N
2
, and N
3
) into a second n-channel region
221
(shown in dashed lines). The reference numbers of the elements of
FIG. 2A
have been incremented by
1
for similar elements in FIG.
2
B. The p-channel
211
and n-channel
221
portions of the circuit are symmetric. In the discussion of the layout of transistors herein below, we focus on a generic layout applicable to both the p-channel
211
and n-channel
221
sections of the sense amplifier. The depiction of a sense amplifier circuit as shown in
FIG. 2B
is more representative of the physical layout of an actual silicon integrated circuit than is the depiction shown in
FIG. 2A
, which is more related to the logical representation of the sense amplifier circuit.
If the size of the DRAM silicon integrated circuit is to be primarily determined by the size of the major component of the integrated circuit, i.e., the array of memory cells, it is incumbent upon the designers of the peripheral components, in this case the sense amplifiers, to make the peripheral component equal or smaller in size than the memory cell. Thus, one seeks ways to make the width of the sense amplifiers no larger that the width of the memory cell, or no larger than the size of a pair of bit lines.
Prior art describes the design of a sense amplifier which uses rows of field effect transistors having a U-shaped gate. Typically such sense amplifiers have a width of greater than 3.5P. This is significantly greater than the size of memory cells which can be fabricated using present memory cell technology, which, as described above, is approximately 2P.
It is desirable to have a sense amplifier which has a width, or pitch, comparable to that of the smallest memory cells which can be produced. Further, it is desirable to have a sense amplifier which does not introduce extra capacitance onto the bit lines. Furthermore, it is desirable to have a sense amplifier which has a simple repetitive, structure, and which does not significantly compromise the cost of the integrated circuits by negatively impacting the photolithographic yield of the integrated circuit.
SUMMARY OF THE INVENTION
The present inventi

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