Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
1999-04-01
2001-02-20
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S205000, C365S207000, C365S230060
Reexamination Certificate
active
06191981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for transmitting a control signal for driving a sense amplifier, and more particularly, to a circuit for controlling a sense amplifier which restores a signal that has been delayed by line loading for faster operation of the sense amplifier, where every one or every group of a few sense amplifiers is provided with one sense amplifier driver for faster data sensing of the sense amplifier.
2. Discussion of the Related Art
The sense amplifier detects, amplifies, and forwards as output a level of voltage or current of a received signal which meets a threshold value during a particular time region. The sense amplifier senses data stored in a memory and the like positively, and amplifies and forwards it as output. In general, the sense amplifier must be highly sensitive, fast, and operative in a wide voltage range, and must have a low power consumption and occupy a small area.
A background art sense amplifier will be explained with reference to the attached
FIGS. 1-3
.
FIG. 1
illustrates a block diagram of a memory, schematically. In
FIG. 1
, the background art memory is provided with an address generating unit
10
for generating an address and an address transition detecting signal ATD, a pre-decoder
20
for decoding the address generated in the address generating unit
10
, a word/bit line decoder
30
for decoding a word line and a bit line in response to a decoded address signal generated in the predecoder
20
, a memory cell
40
adapted to be accessed by a word line (WL) driven by the word/bit line decoder
30
, a sense amplifier
50
for receiving data accessed in the memory cell
40
through bit line BL to amplify a weak signal, and an output latching unit
60
for latching a signal from the sense amplifier
50
in response to the address transition detecting signal ATD generated in the address generating unit
10
.
The operation of the memory device having the aforementioned system will be explained up to the sense amplifier. The address generating unit
10
generates an address transition detecting signal ATD and provides a changed address when an address is changed. Address data from the address generating unit
10
is decoded in the predecoder
20
, which enables a word line WL and a bit line BL relating to the decoded address through the word/bit line decoder
30
, to select an intended memory cell
40
. Then, data received through the enabled bit line BL is amplified in the sense amplifier
50
. In this instance, a data sensing rate of the sense amplifier
50
is a major factor for determining an access rate for the memory.
FIG. 2
illustrates a background art circuit for controlling sense amplifiers in a memory. In
FIG. 2
, the background art circuit for controlling sense amplifiers in a memory is provided with a sense amplifier pull-up driver
51
and a sense amplifier pull-down driver
52
for driving sense amplifiers
50
a
~
50
n
connected to one pair of bit lines BL and /BL representing positive and negative signals, respectively, and a sense amplifier driver precharge circuit
53
for precharging the sense amplifier drivers when the sense amplifiers are not in operation.
FIG. 3
illustrates waveforms of signals at different parts and peripheral important parts in FIG.
2
. The operation between the sense amplifiers having the aforementioned system and the peripheral circuit will be explained with reference to FIG.
3
. When an equalization signal EQ of the sense amplifier driver circuit is at low VSS, signals /SP and SN for controlling a sense amplifier driver are received, driving the sense amplifier drivers
51
-
52
. Thus, sense amplifier drivers
51
and
52
generate /SNC and SPC to drive sense amplifiers
50
a
~
50
n
. When the sense amplifiers
50
a
~
50
n
are driven by /SNC and SPC of the sense amplifier drivers
51
and
52
, the one pair of bit lines of BL and IBL representing a positive signal and a negative signal, respectively, are ready to transmit data.
In this instance, as shown in
FIG. 2
, when there are a plurality of sense amplifiers
50
a
~
50
n
provided therein, if a transmission length of signals /SP and SN for controlling driving of the sense amplifiers
50
a
~
50
n
is long, an accurate signal may not be delivered due to a signal loss caused by the transmission path, i.e., a line loading. Therefore, the background art circuit for controlling a sense amplifier may be susceptible to delays in the operation of the sense amplifier driven by a pull-up or a pull-down operation voltage caused by line loading, which causes major problems for users demanding fast and accurate operation, an ultimately degrades the product.
SUMMARY OF THE INVENTION
The present invention is directed to a circuit for controlling a sense amplifier that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for controlling a sense amplifier which can make an operation of a sense amplifier faster, preferably by recovering signal delay due to line loading.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4948993 (1990-08-01), Chin et al.
patent: 5053998 (1991-10-01), Kannan et al.
patent: 5329492 (1994-07-01), Mochizuki
patent: 5422853 (1995-06-01), Miyamoto
Hyundai Electronics Industries Co,. Ltd.
Le Vu A.
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