Static information storage and retrieval – Read/write circuit – Testing
Patent
1991-08-22
1993-10-26
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
371 211, G11C 700, G11C 2900
Patent
active
052572315
ABSTRACT:
A semicustom-made integrated circuit with built-in memory unit is equipped with an internal timing generator located in the vicinity of the memory unit and responsive to two external controlling signals for producing an internal write enable signal used in a testing mode of operation, and the waveform of the internal write enable signal is hardly deformed on the way to the memory unit even if the signal propagation paths for the external controlling signals are prolonged due to increase of integration density, thereby enhancing the reliability of the testing operation.
REFERENCES:
patent: 4670877 (1987-07-01), Nishibe
patent: 4811299 (1989-03-01), Miyazawa et al.
patent: 4969148 (1990-11-01), Nadeau-Dostie et al.
Dinh Son
LaRoche Eugene R.
NEC Corporation
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