Semiconductor yield estimation

Details Semiconductor yield estimation Semiconductor yield estimation

2005-12-21

2009-02-24

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07496874

ABSTRACT:
A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

REFERENCES:
patent: 5231349 (1993-07-01), Majidi-Ahy et al.
patent: 6102958 (2000-08-01), Meystel et al.
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6317859 (2001-11-01), Papadopoulou
patent: 6324481 (2001-11-01), Atchison et al.
patent: 6715133 (2004-03-01), Brennan
patent: 6771077 (2004-08-01), Hamamura et al.
patent: 6813572 (2004-11-01), Satya et al.
patent: 6941528 (2005-09-01), Allen et al.
patent: 6948141 (2005-09-01), Satya et al.
patent: 7065729 (2006-06-01), Chapman
patent: 7299426 (2007-11-01), Bonges
patent: 2005/0273739 (2005-12-01), Tohyama
patent: 2006/0064653 (2006-03-01), Zhang et al.
patent: 2006/0095877 (2006-05-01), Su et al.
patent: 2006/0190222 (2006-08-01), Allen et al.
patent: 2007/0136714 (2007-06-01), Cohn et al.
Harrison; “A simple via duplication tool for yield enhancement”; Oct. 24-26, 2001; Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on; pp. 39-47.
Allan; “Targeted layout modifications for semiconductor yield/reliability enhancement”;, Nov. 2004; Semiconductor Manufacturing, IEEE Transactions on; vol. 17, Issue 4pp. 573-581.
Yan; “Optimal via minimisation by selection of layer assignment and routing ordering in a bubble-sorting-based non-Manhattan channel”; Jan. 20, 2003: Computers and Digital Techniques, IEE Proceedings-vol. 150, Issue 1, pp. 21-27.
Michalka et al.; “A redundant metal-polyimide thin film interconnection process for wafer scale dimensions”; , Nov. 1990;□□Semiconductor Manufacturing, IEEE Transactions on; vol. 3, Issue4pp. 158-167.
NN950265;“Self-Timed Hit Circuit for a Content Addressable Memory”; Feb. 1995; IBM Technical Disclosure Bulletin;□□vol. No. 2; Issue No. 2; pp. 65-55.
NN9311599; “Displaced Metal Conductor”; Nov. 1993; IBM Technical Disclosure Bulletin; vol. No. 36; Issue No. 11; pp. 599-602.
NN84102880; “Algorithm to Compact a VLSI Symbolic Layout With Mixed Constraints”; Oct. 1, 1984; IBM Technical Disclosure Bulletin; vol. No. 27; Issue No. 5; pp. 2880-2887.

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