Semiconductor with multilayer metal structure using copper...

Details Semiconductor with multilayer metal structure using copper... Semiconductor with multilayer metal structure using copper...

2002-07-05

2003-01-07

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S296000, C438S622000

Reexamination Certificate

active

06504237

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and more particularly to semiconductor logic circuitry having a multilayer wiring structure offering high-speed performances while reducing electrical power consumed therein.
2. Description of the Related Art
Very-large-scale or ultralarge-scale semiconductor logic circuits formed of complementary metal oxide semiconductor (CMOS) transistors are such that semiconductor elements are becoming smaller in size or “shrinking” in minimum feature length. On the contrary, chip sizes are increasing year by year, so electrical interconnect wirings are longer.
As the wirings are longer, electrical resistivity and/or coupling capacitances of the wirings larger than channel resistivities and diffusion layer capacitances of those transistors used to drive the wirings. Thus, device operation speed will no longer be expectable even when semiconductor elements such as transistors are designed to offer enhanced speed performances. This can be because the operation speed of circuitry is determinable by such wirings, resistance and capacitance.
One typical approach to improving the circuit operation speed is to increase wirings thickness and/or width for reduction of their resistances. The approach results in widening a spacing or interval between adjacent wirings. The approach is not suitable for highly integrated logic circuits.
Currently available wirings structures for highly integrated logic circuits include a multilayered wiring structure that comprises a plurality of wirings layers on or over a semiconductor chip. This multilayer structure is typically designed to include two types of wirings layers that are insulatively stacked or laminated at different levels over a semiconductor chip with logic circuits formed thereon. One wiring is local wiring and the other is global wiring. The local wirings are formed in a lower-level layer for electrical interconnection between adjacent ones of the logic circuits on the semiconductor chip. The global wirings are in an upper-level layer for connection between spaced-part ones of the logic circuits (Japanese Patent Publication Unexamined Number 6-13590″).
The logic circuits tend to increase in clock frequency in accordance with microfabrication scaling. Number of wirings in each wiring layer is required to increase in accordance with microfabrication scaling. So even with the above-noted multilayer wiring structure, it can increase in power consumption required for effectuation of capacitive charge-up/discharging at such wiring layer.
Accordingly, it remains difficult for the multilayer wiring structure to reduce the power consumption in wirings capacitance chargeup and discharge events while at the same time improving a wiring delay without having to increase the requisite number of wiring layers.
SUMMARY OF THE INVENTION
The present invention has been made to avoid the problems, and an object of the invention is to provide a semiconductor device capable of suppressing a wiring delay and achieving both low-power consumption and high-speed performances, without accompanying significant changes or modifications of circuit layout of CMOS logic circuitry and wiring structure.
To attain the foregoing object, in accordance with a first aspect of the present invention, a semiconductor device is provided which comprises:
a semiconductor device comprising:
a semiconductor substrate;
a semiconductor element formed on or over the semiconductor substrate, the semiconductor element substantially covered with a first insulating film;
a first wiring formed on the first insulating film, the first wiring electrically connected to the semiconductor element;
a second wiring formed over the first wiring with a second insulating film laid therebetween; and
a third wiring formed over the second wiring with a third insulating film laid therebetween, wherein a thickness of the first wiring is less than a thickness of the second wiring and thickness of the third wiring, and
a distance between the first wiring and the second wiring is greater than a distance between the second wiring and the third wiring.
At this time, it is preferred that the second wiring is formed adjacent and next to the first wiring in an up-down direction, and that the third wiring is formed adjacent and next to the second wiring in the up-down direction.
At this time, it is preferred that when the distance between the first wiring and the second wiring is represented by H
1
while the distance between the second wiring and the third wiring is H
2
, these are given as
H
1
≧1.7×
H
2
.
It is also preferred that a wiring pitch of the adjacent first wirings is less than a wiring pitch of the adjacent second wirings and a wiring pitch of the adjacent third wirings.
It is also preferred that a wiring width of the first wiring is less than a wiring width of the second wiring and a wiring width of the third wiring.
It is also preferred that the first wiring and the second wiring are in a relation of crossover layout.
It is also preferred that an amplitude of a signal voltage of the second wirings and an amplitude of a signal voltage of the third wirings are each less than an amplitude of a signal voltage of the first wirings.
It is also preferred that the amplitude of the signal voltage of the first wiring is equal to a difference between a power supply voltage of the semiconductor element V
DD
and a grand voltage.
It is also preferred that when the amplitude of the signal voltage of the second wiring is V
1
, the distance between the first wiring and the second wiring is greater than (V
DD
/V
1
)
1.5
times of the distance between the second wiring and the third wiring.
It is also preferred that the first wiring is directly connected to the semiconductor element through a contact hole.
It is also preferred that
19
the amplitude of the signal voltage of the second wirings is less than or equal to 0.48V
DD
.
In addition, in accordance with a second aspect of the invention, a semiconductor device is provided which comprises:
a semiconductor device comprising:
a semiconductor substrate;
a semiconductor element formed on or over the semiconductor substrate, the semiconductor element substantially covered with a first insulating film;
a first wiring formed on the first insulating film, the first wiring electrically connecting to the semiconductor element;
a second wiring formed over the first wiring with a second insulating film laid therebetween;
a third wiring over the second wiring with a third insulating film laid therebetween; and
a fourth wiring formed over the third wiring with a fourth insulating film laid therebetween,
wherein a thickness of the first wiring is less than a thickness of the second wiring, the third wiring and the fourth wiring, and
a distance between the first wiring and the second wiring is greater than a distance between the third wiring and the fourth wiring.
At this time, it is preferred that the second wiring is formed adjacent and next to the first wiring in an up-down direction, that the third wiring is formed adjacent and next to the second wiring in the up-down direction, and that the fourth wiring is formed adjacent and next to the third wiring in the up-down direction.
At this time, it is preferred that when the distance between the first wiring and the second wiring is represented by H
1
while the distance between the third wiring and the fourth wiring is H
2
,
 
H
1
1.7×
H
2
is established.
It is also preferred that a wiring pitch of the adjacent first wirings is less than a wiring pitch of the adjacent second wirings and a wiring pitch of the adjacent third wirings.
It is also preferred that a wiring width of the first wiring is less than a wiring width of the second wiring and a wiring width of the third wiring.
It is also preferred that a wiring pitch of the adjacent first wirings is less than a wiring pitch of the adjacent fourth wirings.
It is also preferred that the first wiring and the second wiring are in a relation of cro

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