Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-06-26
2010-12-28
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S110000, C438S112000, C438S458000, C438S459000, C438S460000, C257S741000, C257S735000, C257S774000
Reexamination Certificate
active
07858512
ABSTRACT:
A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.
REFERENCES:
patent: 4673967 (1987-06-01), Hingorany
patent: 5910687 (1999-06-01), Chen et al.
patent: 6051489 (2000-04-01), Young et al.
patent: 6221751 (2001-04-01), Chen et al.
patent: 6355981 (2002-03-01), Richards et al.
patent: 6441487 (2002-08-01), Elenius et al.
patent: 6521970 (2003-02-01), Takiar et al.
patent: 6589819 (2003-07-01), Smith et al.
patent: 6638870 (2003-10-01), Brintzinger et al.
patent: 6946734 (2005-09-01), Marcoux et al.
patent: 7205659 (2007-04-01), Beroz et al.
patent: 7622810 (2009-11-01), Takao
patent: 9129675 (1997-05-01), None
patent: 2000003976 (2000-01-01), None
patent: 1020000070442 (2000-11-01), None
patent: 9852224 (1998-11-01), None
Verdant Electronics, Inc. “Robust, Simplified and Solder-Free Assembly Processing of Electronics Products”, Sunnyvale, California, 24 Pages.
W.E. Jahsman et al., Comparison of Predicted and Measured Lead Stiffness of Surface Mounted Packages, Intel Corporation, Electronic Components and Technology Conference, 1990 Proceedings, 40th, vol. 2, pp. 926-932 (May 20-23, 1990).
ATMEL, 64K (8K x 8) Parallel EEPROMs; AT28C64, AT28C64X, Dec. 1999, 12 pages.
Texas Instruments, TM124MBK36F, TM124MBK36U, 1048576 by 36-Bit DRAM Module; TM248NBK36F, TM248NBK36U 2097152 by 36-Bit DRAM Module.
Diallo Mamadou
Heller III Edward P.
Richards N Drew
Wafer-Level Packaging Portfolio LLC
LandOfFree
Semiconductor with bottom-side wrap-around flange contact does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor with bottom-side wrap-around flange contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor with bottom-side wrap-around flange contact will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4151346