Semiconductor wiring technique for reducing electromigration

Details Semiconductor wiring technique for reducing electromigration Semiconductor wiring technique for reducing electromigration

1997-10-06

2001-10-23

Teska, Kevin J. (Department: 2123)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06308302

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic design automation (EDA) tools for integrated chip (IC) wiring design. In particular, this invention provides the capability for EDA tools to effectively deal with electromigration (EM) degradation of IC circuits, thereby providing placement and wiring output that avoids IC performance and reliability problems associated with EM.
BACKGROUND OF THE INVENTION
The following definitions apply throughout the following specification. The term placement in the following specification refers to assignment of exact locations to circuits or the assignment of circuits to regions of the IC. A circuit is a an element which may be used multiple times on an IC. It is typically an element of a technology circuit library. A circuit instance is a unique instance of a circuit on an IC. Each circuit instance of a particular circuit will have a different placement and different connections to its pins (nets). A net represents a connection which must be made between sets of source and sink pins on an IC. A wire is a set of connected conductors which form the connection represented by a net. A wire segment (or segment) is a contiguous (generally straight) region of a single conducting layer of an IC which is a portion of a wire. A via is a conductor which forms a connection between different conducting layers of an IC, and which is a portion of a wire. A pin is a conducting region of a circuit instance to which a wire is connected.
IC wiring is subject to various degradation phenomena caused by electronic interaction with metal atoms, particularly at metallic grain boundaries. The rate of degradation increases with current density. If the current density can be kept below a conductor-specific threshold, degradation can be rendered negligible for the life of any particular IC circuit. EM effects become more prominent as IC frequencies increase and IC feature sizes decrease.
Prior art EM checking tools identified wired circuit errors for the circuit designer who manually input corrections to any erroneous IC circuit net, such as widening the wires in an entire net. These tools did not embody any automatic correction capability. Overdesign, i.e., overwidth, for worst case EM estimates was required which wasted valuable chip space. On the other hand, wiring nets with a minimum size wire to determine the route, and then widening the wire segments as needed may result in electrical shorts to other nets, circuits, and power buses.
No IC analysis tools took into account the capacitance of the wire segment itself in determining the width of wires that should be used, and focused only on pin capacitances and capacitance added by pre-wiring structures.
A number of factors contribute to whether an EM problem exists on an IC net. These include: the amount of current that flows through the net during switching, the switching frequency of the net, physical properties of the wire segments, operating temperature, proximity of functional circuit areas, and an anticipated lifespan of the IC.
One way to avoid the maximum current density threshold is to reduce the current passing through a wire. Another way is to increase the cross section of the wire. Yet another way to reduce current density is to minimize capacitive effects of the wiring which tend to maximize current density at an end of a wire segment nearest the current source. The capacitive effects are dependent upon the layout of the various IC components. Thus, a better designed layout can also contribute to a reduction in capacitive effects which, in turn, reduces current density.
Simple methods of addressing EM problems such as designing wider wire widths across all the IC nets result in problems such as wasted wiring space when a wide wire is used unnecessarily for an entire net. This is because the EM problem gets progressively less severe as one moves from the source pin of a net out to each of the sink pins, and wide wires are very often not needed as one moves closer to the sink pins. Also, it may be true that only a segment, or only a via, of a wiring net need be widened to eliminate EM problems for the whole net. Capacitance measurements were made but only as an intermediate final result output for a wired circuit. None of the prior art includes the capability disclosed herein to narrow wires and to analyze the results of the narrowing automatically and immediately.
The amount of current flowing through all upstream wire segments increases as the width of a given wire segment increases. This is because as a wire segment is widened its capacitance is increased, however, the rate at which current density decreases is much greater than the rate of capacitance increase. This is an important factor since increased capacitance alone will require increased driving current.
In the absence of DC loads, current drawn through a wire segment resulting from a signal transition is determined by the downstream capacitive load driven by that wire segment. The wire width that will satisfy EM requirements for a wire segment cannot be exactly determined until the route between the wire segment and all downstream sinks is determined and all downstream wire widths are known.
In general, EDA tools have automated circuit layout without automatically incorporating critical reliability criteria. Commercially available electronic design automation tools typically develop placement and wiring output in several identifiable steps. These tools take as input a list of circuit definitions. These circuits may be repeated multiple times in the circuit design. The circuit definitions, i.e., the “netlist”, might include information such as a label to identify a circuit to be selected from a library of defined circuits. Each of the definitions may specify a number of connections required for the particular circuit together with other electrical constraints, a list of other circuits that need to be attached, particular data lines that must be connected, usages of other library elements, chip area blocked by the circuit, signal characteristics, size, pin locations, capacitance constraints, etc. Required connections to other defined circuits may also be specified. An amount of space occupied by a functional circuit may be specified. Chip image information may delineate where circuits can be placed, where wiring can be placed, etc. Typically, alternative constraints may be added by the user of the tool to the core definitions stored in the library.
The netlist is fed into a placement tool which outputs a general placement topology for the circuit elements. This placement topology is relayed to a wiring tool which lays down a wiring plan for the IC based on the information specified in the circuit library. The wiring may be accomplished in two steps: a global wiring pass followed by a final detailed wiring. An EM check is usually performed at this point to check for EM problems. If a problem exists, the designer typically must choose which nets to widen in order to pass the EM check. This process might require numerous iterations requiring the designer's attention at every iteration.
SUMMARY OF THE INVENTION
To improve physical properties of wire segments, the present invention selectively uses wider wiring as required. Since the RC delay of a net is also affected by wire width, performance optimization in regard to timing is an additional objective of this process. Thus, RC measurements can be used as design constraints to improve circuit timing.
The present invention addresses current density problems by employing techniques that allow EM effects to be considered by automatic circuit design tools. This is accomplished through use of capacitance targets based on EM criteria. Capacitance targets are used because the downstream capacitive load on any wire segment controls how much current will flow through it.
The present invention optimizes wiring widths and, therefore, consumed chip area, based on iteratively reducing wire widths during global and detailed wiring routines. IC circuit nets which require special handling for EM

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