Semiconductor wafer with improved crack protection

Details Semiconductor wafer with improved crack protection Semiconductor wafer with improved crack protection

2007-01-29

2010-06-22

Lee, Hsien-ming (Department: 2823)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S465000, C257SE21599

Reexamination Certificate

active

07741196

ABSTRACT:
A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

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