Semiconductor wafer testing method and apparatus

Details Semiconductor wafer testing method and apparatus Semiconductor wafer testing method and apparatus

1996-01-16

1998-05-26

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257 81, 372 38, 372 50, H01L 2358, H01S 319

Patent

active

057570272

ABSTRACT:
The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.

REFERENCES:
patent: 5317587 (1994-05-01), Ackley et al.
patent: 5388120 (1995-02-01), Ackley et al.
patent: 5446751 (1995-08-01), Wake
patent: 5500867 (1996-03-01), Krasulick

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