Semiconductor wafer structure with balanced reflectance and...

Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure

Reexamination Certificate

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C438S761000, C257SE21211

Reexamination Certificate

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08080465

ABSTRACT:
Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate. Methods of forming a semiconductor structure begin by forming a substrate, forming an insulator layer on the substrate, and forming a first film on a first portion of the insulator layer. Methods form a second film, different from the first film, on a second portion of the insulator layer adjacent to the first film such that a first net reflectivity of the first film, the insulator layer, and the substrate is approximately equal to a second net reflectivity of the second film, the insulator layer and the substrate.

REFERENCES:
patent: 4525380 (1985-06-01), Arai et al.
patent: 5336641 (1994-08-01), Fair et al.
patent: 5523262 (1996-06-01), Fair et al.
patent: 5841110 (1998-11-01), Nenyei et al.
patent: 5897381 (1999-04-01), Aronowitz et al.
patent: 5956603 (1999-09-01), Talwar et al.
patent: 6015745 (2000-01-01), Adkisson et al.
patent: 6262435 (2001-07-01), Plat et al.
patent: 6300243 (2001-10-01), Thakur
patent: 6403923 (2002-06-01), Tay et al.
patent: 6414364 (2002-07-01), Lane et al.
patent: 6569720 (2003-05-01), Kunii
patent: 6665858 (2003-12-01), Miyazaki
patent: 6812550 (2004-11-01), En et al.
patent: 6867080 (2005-03-01), Paton et al.
patent: 6875623 (2005-04-01), Niwayama et al.
patent: 6916690 (2005-07-01), Chang
patent: 7071530 (2006-07-01), Ding et al.
patent: 7344929 (2008-03-01), Mehrotra et al.
patent: 7589027 (2009-09-01), Lee
patent: 7745334 (2010-06-01), Press et al.
patent: 7871895 (2011-01-01), Divakaruni et al.
patent: 2004/0033666 (2004-02-01), Williams et al.
patent: 2004/0077149 (2004-04-01), Renau
patent: 2004/0084427 (2004-05-01), Talwar et al.
patent: 2004/0188801 (2004-09-01), Ehrichs
patent: 2004/0195626 (2004-10-01), Yamada et al.
patent: 2004/0259387 (2004-12-01), Yamazaki et al.
patent: 2005/0003638 (2005-01-01), Stolk
patent: 2005/0009344 (2005-01-01), Hwang et al.
patent: 2005/0059224 (2005-03-01), Im
patent: 2005/0085047 (2005-04-01), DeLoach et al.
patent: 2005/0173802 (2005-08-01), Tabara et al.
patent: 2005/0189340 (2005-09-01), Talwar et al.
patent: 2005/0191044 (2005-09-01), Aderhold et al.
patent: 2006/0099745 (2006-05-01), Hsu et al.
patent: 2006/0154475 (2006-07-01), Mehrotra et al.
patent: 2006/0228897 (2006-10-01), Timans
patent: 2007/0063223 (2007-03-01), Choi
patent: 2007/0069293 (2007-03-01), Kavalieros et al.
patent: 2007/0230553 (2007-10-01), Talbot et al.
patent: 2008/0230843 (2008-09-01), Zhang et al.
patent: 2009/0302414 (2009-12-01), Ebefors et al.
patent: 10329212 (2005-01-01), None
patent: 06-295923 (1994-10-01), None
patent: 2206141 (2003-06-01), None
patent: 9319484 (1993-09-01), None
patent: 2007038575 (2007-04-01), None
Anderson et al., U.S. Appl. No. 12/719,153, Office Action Communication, Jan. 10, 2011, 17 pages.
Anderson et al., U.S. Appl. No. 12/719,153, Office Action Communication, Jul. 23, 2010, 15 pages.
Laviron et al., “Intra-Die Temperature Non Uniformity Related to Front Side Emissivity Dependence during Rapid Thermal Annealing”, 203rd ECS Meeting, Paris, Apr. 27-May 2, 2003, paper #880, pp. 1-9.
Anderson et al., U.S. Appl. No. 11/678,783, Office Action Communication, Apr. 30, 2009, 12 pages.
Anderson et al., U.S. Appl. No. 11/678,745, Office Action Communication, May 13, 2009, 19 pages.
Anderson et al., U.S. Appl. No. 11/869,768, Office Action Communication, May 14, 2009, 26 pages.
PCT International Search Report and Written Opinion dated Aug. 27, 2009, pp. 1-12.
Anderson et al., U.S. Appl. No. 11/869,768, Office Action Communication, Nov. 24, 2009, 5 pages.
Anderson et al., U.S. Appl. No. 11/678,745, Notice of Allowance, Nov. 18, 2009, 10 pages.
Anderson et al., U.S. Appl. No. 11/678,799, Notice of Allowance, Feb. 17, 2010, 4 pages.
Anderson et al., U.S. Appl. No. 11/678,799, Office Action Communication, Apr. 15, 2009, 19 pages.
Anderson et al., U.S. Appl. No. 11/678,799, Office Action Communication, Oct. 27, 2009, 15 pages.
Anderson et al., U.S. Appl. No. 11/678,756, Notice of Allowance, Mar. 15, 2010, 3 pages.
Anderson et al., U.S. Appl. No. 12/719,153, Office Action Communication, Apr. 14, 2011, 16 pages.
Anderson et al., U.S. Appl. No. 12/719,153, Notice of Allowance, Aug. 8, 2011, 12 pages.

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