Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1998-12-04
2002-10-08
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C029S025010, C414S225010, C118S500000, C118S725000
Reexamination Certificate
active
06462411
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor wafer processing apparatus, and more particularly, to a diffusion apparatus for oxidizing or annealing a wafer used in a semiconductor device manufacturing process, and a semiconductor wafer processing apparatus utilizing a thermal CVD (Chemical Vapor Deposition) for forming, on a wafer surface, a metal film, a metal silicide film, an oxide film, a nitride film, a poly-crystalline silicon film, a dielectric film or an epitaxial silicon film or the like, and the present invention especially relates to a hot wall type single wafer or couple of wafers substrate processing type oxidizing apparatus and a single wafer or couple of wafers processing type CVD method which do not generate slip lines due to thermal stress.
2. Description of the Related Art
At present, a batch type apparatus (a vertical-type diffusion apparatus, a vertical-type CVD apparatus) is mainly used for a semiconductor thermal treatment process such as oxidization, anneal and thermal CVD. However, in order to cope with a high integration tendency of a semiconductor device, a technique for forming a very thin oxide film of about a couple of nanometers or a shallow diffusion layer, and a technique for preventing a natural oxidation are indispensable.
To meet these requirements, a single wafer or small number of wafers processing apparatus suitable for short time processing shorter than a couple of minutes is advantageous. Further, there is a merit that this single wafer or small number of wafers processing apparatus can easily cope with clustering unit or a larger diameter tendency of a wafer. On the other hand, it has been found that there is a problem in a manufacturing line in which a batch type apparatus and a single wafer or small number of wafers processing apparatus (an etching apparatus, a sputtering apparatus and so forth) are mixed in view of the fact that a semiconductor device cannot be manufactured within a short time. Therefore, a single wafer or small number of wafers processing thermal treatment apparatus becomes indispensable.
In the above described single wafer or small number of wafers processing thermal treatment apparatus, rapid heating is indispensable for improving a throughput. In that case, however, there is a problem that slip lines are generated due to thermal stress by temperature deviation within a wafer face. To cope with this problem, various methods have been studied and proposed to reduce slip lines with lamp annealing apparatus which heals a wafer at 1,000° C. or higher within tens of seconds mainly using halogen lamp or ark lamp. Examples of such methods are shown below.
Japanese Patent Application Laid-open No.6-163444 (Conventional Art
1
) discloses a technique to dispose a wafer such that an orientation flat of the wafer opposes to an opening of a guard ring, and heat the wafer using a lamp, and a technique to provide an auxiliary ring connected to opposite ends of the guard ring such as to bypass the opening of the guard ring. The wafer and the guard ring are held substantially flush with each other by a pin holder.
The above conventionally known art is for suppressing or preventing slip lines from being generated on a wafer in a lamp annealing apparatus. The lamp annealing apparatus to which this conventional art is applied has a merit that the wafer can be heated within a short time. On the other hand, as compared with the batch type thermal treatment apparatus, there are problems that uniformity of temperature of wafers is inferior, consumption of electricity is greater, and a lifetime of the lamp is short.
Japanese Patent Application Laid-open No.2-69932 (Conventional Art
2
) disclosed by the present inventors discloses a semiconductor wafer thermal treatment apparatus as a single wafer or small number of wafers processing thermal treatment apparatus in which the above problems are overcome. This is a vertical-type single wafer or small number of wafers processing thermal treatment apparatus, in which a plurality of wafers are substantially vertically held on a transfer jig having function for both supporting and transferring the wafers, the wafers are inserted at a high speed into a reaction furnace provided at its lower portion with an insertion opening and a retrieving opening, and the wafers are oxidized or annealed. In the above mentioned former lamp anneal apparatus, after the wafer is inserted into a reaction furnace, the lamp is electrically conducted to start heating the wafer. Whereas, in the latter conventional apparatus, the heater is always electrically conducted to keep the reaction chamber at a high temperature (hot wall type), and the wafers are inserted at a high speed and processed. Therefore, there are merits that uniformity of temperature of wafers is excellent, consumption of electricity is small, and lifetime of the heater is long. However, as in the lamp anneal apparatus, the hot wall type single wafer or small number of wafers processing thermal treatment apparatus also has a problem that slip lines are generated due to thermal stress by temperature deviation within the wafer face. That is, since the latter conventional apparatus simultaneously processes the two wafers, the center of each of the wafers is heated only from its one side facing the heater but the edge of each of the wafers is also heated by radiation entering from clearances among wafers and therefore, temperature of the outer side of the wafer rises faster than the inner side of the wafer. In the latter conventional application, there is disclosed a technique to relatively retard the temperature rise of the wafer edge by providing rings among or outside the two wafers supported on the transfer jig.
As a CVD apparatus which keeps the merit of the above mentioned vertical-type single wafer or small number of wafers processing thermal treatment apparatus, and which makes it easy to use the apparatus as a cluster unit, there is a known single wafer or small number of wafers processing CVD apparatus for horizontally-holding a plurality of wafers for processing. This single wafer or small number of wafers processing CVD apparatus is disclosed in Japanese Patent Application Laid-open No.7-94419 (Conventional Art
3
). A structure of a reaction furnace of this single wafer or small number of wafers processing CVD apparatus will be explained with reference to
FIGS. 15
to
17
b
.
FIG. 15
is a cross-sectional view of the reaction furnace of the conventional single wafer or small number of wafers processing CVD apparatus as viewed from above.
FIG. 16
is a vertical cross-sectional view of the reaction furnace of the conventional single wafer or small number of wafers processing CVD apparatus as viewed side.
FIGS. 17
a
and
17
b
are vertical cross-sectional views of the reaction furnace of the conventional single wafer or small number of wafers processing CVD apparatus as viewed from side for showing a supporting method of wafers in the reaction furnace. The apparatus is provided at its upper and lower portions with flat heaters
1
each divided into a plurality of zones, and a reaction tube
2
is disposed between the upper and lower heaters
1
. Two wafers
3
in a horizontal state are inserted and heated. While a gas is supplied from a gas supply port
4
(
4
a
,
4
b
), the gas is discharged from an exhaust port
5
(
5
a
,
5
b
) disposed opposite side from the gas supply port
4
(
4
a
,
4
b
) (gas flows in parallel to the wafers
3
as shown by white or black arrow in the drawings), thereby forming films on the wafers
3
. Abase
20
is disposed in the reaction tube
2
, and supporting plates
8
a
and
8
b
for supporting the wafers
3
thereon are provided on the base
20
. The supporting plates
8
a
and
8
b
are positioned at substantially central portion of the reaction tube
2
. Supporting plate holding pins
22
are provided on the base
20
at four corners of the supporting plates
8
a
and
8
b
. Each of the supporting plate holding pins
22
is formed such that its t
Ikeda Fumihide
Inokuchi Yasuhiro
Inoue Yohsuke
Mise Nobuyuki
Sakurai Yoshihiko
Chambliss Alonzo
Kokusai Electric Co., LTD
Talbott David L.
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