Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1998-12-02
2002-07-16
Boudreau, Leo (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
C382S147000
Reexamination Certificate
active
06421456
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor wafer and a method for sawing the wafer, and more particularly to a semiconductor wafer which has recognition marks on the points where vertical and horizontal scribe lines cross each other, and a method for sawing the wafer using the recognition marks.
2. Description of the Related Arts
The integrated circuit manufacturing process is divided into several steps such as circuit fabrication, assembly, and testing. The circuit fabrication forms integrated circuits on a semiconductor wafer. After fabrication, the first step of assembly is wafer sawing which divides the wafer into a plurality of individual integrated circuit chips.
Referring to
FIG. 1
, a wafer
10
comprises a plurality of semiconductor chips
12
having integrated circuits formed thereon. Semiconductor chips
12
are separated from each other by a plurality of vertical and horizontal scribe lines
14
and
16
, respectively. Scribe lines
14
and
16
have no circuitry, and a sawing process cuts the wafer
10
along scribe lines
14
and
16
. The width of vertical and the horizontal scribe lines
14
and
16
have typical widths of about from 5 to 7 mils.
Referring to FIG.
2
through
FIG. 4
, a method for using a wafer sawing apparatus
70
to saw wafer
10
will be described. The wafer
10
is loaded on a wafer aligning stage
72
of wafer sawing apparatus
70
. Then, alignment and sawing of wafer
10
are carried out.
FIG. 2
depicts wafer sawing where saw blade
74
is aligned along a horizontal scribe line
16
.
In aligning wafer
10
for sawing, a recognition means such as a camera
76
recognizes any two spots on wafer
10
, and a control part
28
uses the spots as references when aligning one of horizontal scribe lines
16
of wafer
10
under saw blade
74
.
The next step is an inspection of whether horizontal scribe line
16
is properly aligned under saw blade
74
. With reference to FIG.
2
and
FIG. 3
, camera
76
images an area A of an integrated circuit pattern on a semiconductor chip
12
on wafer
10
, (hereinafter, the pattern in area A being referred to as a “standard pattern”) and transfers the image of area A to a control unit
78
. Control unit
78
uses the image of area A as a reference image in subsequent alignment inspection.
Other semiconductor chips
12
on the wafer
10
have the same patterns as the standard pattern. Camera
76
images nine areas A to I of the semiconductor chips
12
and transmits the image of each area to control unit
78
. The distance between adjacent areas are known according to the size of semiconductor chips
12
. The image of area A indicates the standard pattern and areas B to I should contain the same pattern if wafer
10
is properly aligned. The reference image of area A is given a recognition value of
100
, and the recognition values of the nine spots A to I are calculated based on the images from camera
76
as displayed on a monitor
77
of the control unit
78
. If all recognition values of the spots A to I are greater than a judgment value, control unit
78
decides that wafer
10
is properly aligned. However, if any of the recognition values of areas A to I is less than the judgment value, control unit
78
decides that wafer
10
is not properly aligned. A typical judgment value is
70
.
The above-described wafer alignment method is referred to as a Pattern Matching System (PMS) method, and adopted in a model DFD-640 wafer sawing apparatus which was developed by DISCO. Another wafer alignment method is the Pattern Recognition System (PRS) method. This method is adopted in a model SD02-8W wafer sawing apparatus which was developed by SEICO SEIKI. The PMS method recognizes integrated circuit patterns of the wafer by classifying them into two colors, black and white, but the PRS method recognizes the patterns by classifying them into 256 colors.
An operator of sawing apparatus
10
chooses a spot (area A) on a semiconductor chip
12
for a reference pattern by his/her own judgment. With reference to
FIG. 4
, since camera
76
(
FIG. 2
) recognizes integrated circuit patterns by brightness of the patterns, a spot which has features that are easily distinguished from other patterns by the brightness recognition, is ideally designated as a reference spot.
With the above methods, the reference spot and other spots recognized for alignment inspection are parts of semiconductor chips
12
. Since the recognized spots are not the area to be sawn, it is necessary to correct the position of the wafer
10
so that the scribe lines
14
and
16
are aligned under the saw blade
74
, based on the relative position of the recognized spots to scribe lines
14
and
16
. Dotted lines
18
on vertical and horizontal scribe lines
14
and
16
are where saw blade
74
(
FIG. 2
) contacts and saws wafer
10
.
A reference numeral
20
in
FIG. 4
indicates a window, that is, an area in which camera
76
(
FIG. 2
) recognizes the pattern. The position of the camera
76
is adjusted using a vertical line
26
and a horizontal line
28
of window
20
. In
FIG. 4
, features
15
are hatched differently to indicate a difference in the brightness of features
15
.
Table 1 shows the recognition values of the nine areas A to I on wafer
10
, the judgment based on the recognition values, and the decision regarding an exemplary wafer sawing operation.
TABLE 1
Spot
A
B
C
D
E
F
G
H
I
Recog-
91
79
94
97
98
93
65
50
90
nition
value
Judg-
OK
OK
OK
OK
OK
OK
bad
bad
OK
ment
Opera-
alignment failure/wafer sawing mistake
tion
Area A is the reference pattern as described above. The reason that the recognition values of areas A to I are not 100 is that the recognized image from each spot is not exactly the same as the reference image initially taken from spot A due to small mechanical operation error of camera
76
. However, the recognition values less than 70 for areas G and H means that the patterns recognized in areas G and H are different from the pattern in area A, and thereby wafer
10
is misaligned. A problem occurs when wafer
10
is misaligned, but the recognition values are greater than 70 because each semiconductor chip
12
contains multiple copies of the reference pattern or a similar pattern. For example, when camera
76
recognizes the pattern in window
24
due to the wafer misalignment, the recognition value from the spot in window
24
can be greater than 70 because of a little difference between the patterns of spot A and the spot in window
24
. This misalignment can make saw blade
74
cut wafer
10
across semiconductor chips
12
, not along scribe lines
14
and
16
. Furthermore, if wafer
10
includes different kinds of semiconductor chips
12
, wafer alignment process becomes complicated because respective reference spots are designated for different chips
12
.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor wafer on which standardized recognition marks are formed and a wafer sawing method using the recognition marks.
Another object of the present invention is to provide a semiconductor wafer having standard recognition marks which prevent the wafer sawing failure due to wafer misalignment and a wafer preparation method for semiconductor wafer sawing. The preparation method comprises formation of standard recognition marks on the wafer and sawing the wafer by using the standard recognition marks for alignment of the wafer.
In order to achieve the foregoing and other objects, the present invention provides a semiconductor wafer comprising a plurality of semiconductor chips, a plurality of scribe lines including horizontal scribe lines and vertical scribe lines, and standard recognition marks formed at the points where the horizontal and the vertical scribe lines cross each other. Particularly, the standard recognition marks of the present invention have patterns which can be easily and clearly recognized by the camera during the semiconductor wafer aligning for wafer sawing. For example,
Kim Byung Man
Lee Youn Soo
Son Dae Woo
Boudreau Leo
Chawan Sheela
Heid David W.
Samsung Electronics Co,. Ltd.
Skjerven Morrill LLP
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