Semiconductor wafer level package

Details Semiconductor wafer level package Semiconductor wafer level package

1991-12-16

1994-06-21

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Physical deformation

257419, 257693, H01L 2302

Patent

active

053230515

ABSTRACT:
A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer is bonded to the semiconductor substrate wafer using a pre-patterned frit glass as a bonding agent such that the device is hermetically sealed inside a cavity. A hole in the cap wafer allows electrical connections to be made to the device through electrodes which pass through the frit glass seal.

REFERENCES:
patent: 3768157 (1973-10-01), Buie
patent: 4477828 (1984-10-01), Scherer
patent: 4791075 (1988-12-01), Lin
patent: 4802952 (1989-02-01), Kobori et al.
patent: 4907065 (1990-03-01), Sahakian
patent: 5121180 (1992-06-01), Beringhause

Affiliated with

Also associated with

Rating

Semiconductor wafer level package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor wafer level package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor wafer level package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2222664