Semiconductor wafer having a layer-to-layer alignment mark and m

Details Semiconductor wafer having a layer-to-layer alignment mark and m Semiconductor wafer having a layer-to-layer alignment mark and m

1999-05-13

2000-10-24

Dutton, Brian

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

438427, 438622, 438692, 438975, H01L 2176, H01L 214763, H01L 21302

Patent

active

061366625

ABSTRACT:
A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.

REFERENCES:
patent: 5343292 (1994-08-01), Brueck et al.
patent: 5525840 (1996-06-01), Tominaga
patent: 5559601 (1996-09-01), Gallatin et al.
patent: 5596413 (1997-01-01), Stanton et al.
patent: 5786116 (1998-07-01), Rolfson
patent: 5847468 (1998-12-01), Nomura et al.
patent: 5985764 (1999-11-01), Lin et al.
patent: 6046094 (2000-04-01), Jost et al.
patent: 6046101 (2000-04-01), Dass et al.

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