Semiconductor wafer fabrication

Details Semiconductor wafer fabrication Semiconductor wafer fabrication

1999-09-23

2001-05-29

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S761000

Reexamination Certificate

active

06239035

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the manufacture of semiconductor wafers and more specifically to improving semiconductor device yield by reducing particle defects.
BACKGROUND OF THE INVENTION
In a typical wafer fabrication process device defects are frequently caused by metal particulates produced during the patterning of the metal layers and the interlevel dielectric layers. Particulates are produced from a variety of sources but an especially troublesome source is the edge of the wafer where the edge of a completed metal layer may be exposed during subsequent processing. The problem is exacerbated by the conventional edge bead removal procedure which exposes prior metal levels and allows edge debris from those prior metal levels to deposit on the wafer during fabrication. This metal edge debris causes shorts in the integrated circuit being formed. These shorts are detected after processing of the integrated circuit is completed and much of the cost of processing these defective devices is wasted.
SUMMARY OF THE INVENTION
Recognizing this problem I have developed a technique for ensuring that the edges of metal levels remain covered during the entire process sequence, thus preventing metal edge debris from forming. This goal is achieved by burying the metal edges in the interlevel dielectrics. This “buried edge” process protects each underlayer as new levels are formed, and prevents exposure of previously formed metal edges even during window etch. According to the invention this result is achieved by etching a peripheral ring at the edge of the wafer in each metal level, and depositing each interlevel dielectric so that it covers the edge of underlying metal layer. A peripheral ring at the edge of the wafer in each interlevel dielectric layer is also removed, but the width of the ring of interlevel dielectric material removed is smaller than the width of the ring of metal removed so that each interlevel dielectric layer extends closer to the wafer edge than the metal layers, thereby insuring that the edge of each metal layer is buried. The objective in this embodiment is to leave the periphery of the wafer devoid of layer buildup so that during wafer handling and clamping there is no deposited material to chip off and form debris. The technique described essentially replaces the edge bead removal process that is typically used in wafer fabrication.
In removing the peripheral ring of each metal layer, the size of the peripheral ring in each sequential metal layer is decreased, which results in a tapered step thus further ensuring that the edge of each metal layer is well protected during subsequent processing.


REFERENCES:
patent: 5618380 (1997-04-01), Siems et al.

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