Radiant energy – Photocells; circuits and apparatus – With circuit for evaluating a web – strand – strip – or sheet
Reexamination Certificate
2002-06-20
2004-03-23
Le, Que T. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
With circuit for evaluating a web, strand, strip, or sheet
C250S566000
Reexamination Certificate
active
06710364
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuit manufacture, and is more specifically directed to the identification and orientation of semiconductor wafers throughout the manufacturing process.
As is fundamental in the art, modern semiconductor integrated circuits are fabricated at the surface of a wafer of semiconductor material such as single-crystal silicon. Each circuit, which is referred to as a “die” when in chip form, is at a position within an array of die at the wafer surface, so as to be fabricated simultaneously with the other die on that wafer. Since some manufacturing processes, such as thermal oxide growth, cleanups, and the like are performed simultaneously for multiple wafers, the wafers are also generally grouped into lots during the manufacturing processes. Other processes, such as photolithography, plasma etch, and the like are generally performed on a wafer-by-wafer basis.
Because all of the die on a given wafer are processed substantially identically relative to one another, many of their electrical characteristics will be substantially similar. Similarly, to the extent that the wafers in a lot are fabricated by batch processes, some of the electrical characteristics of the integrated circuits on different wafers within the same lot will also be quite similar. Additionally, most wafer fabrication factories maintain data regarding the date, time, manufacturing operators, and processing parameters (temperatures, times, gases and liquids used, process equipment used, etc.) according to which each wafer and each lot are manufactured. It is therefore useful to identify each lot, and each wafer within the lot, during the manufacture and electrical testing of the integrated circuits, so that electrical and manufacturing yield, as well as electrical performance of the eventual integrated circuits, may be correlated to this process information. Additionally, the identification of wafers within lots has now permitted the order of wafers within the lot to be randomized at certain manufacturing processes, facilitating the analysis of the dependence of integrated circuit yield and performance upon process parameters.
It has therefore become commonplace in the manufacture of integrated circuits to mark wafers with some type of identifier, generally a lot identifier and a wafer identifier. These identifiers are conventionally marked on the front surface of the wafer (i.e., the wafer surface at which the integrated circuits are being formed). A typical method of marking the lot identifier on a semiconductor wafer is by laser marking, where the laser locally melts the semiconductor in a pattern corresponding to the lot number and wafer number; recrystallization of the locally melted semiconductor then provides a permanent identifier upon the wafer surface.
The particular format of the lot and wafer identifiers can vary widely, depending primarily upon the manner in which the identifiers are to be read. In years past, the lot and wafer numbers were simply marked as human readable numerals, visible to the naked eye. Recently, various coded formats have been used so that the lot and wafer identifiers are machine readable. For example, the BC412 bar code symbology, which utilizes a linear or “1-D” bar code, has recently become accepted as a standard for wafer marking by SEMI.
Additionally, the manufacturer of the semiconductor wafers that are to be used in the manufacture of integrated circuits (i.e., the starting material for the wafer fabrication factory) will also include certain marks on the wafers. These marks may correspond to lot or batch numbers by way of which the starting material was fabricated, for example a number corresponding to the pulled crystal ingot of semiconductor from which the particular wafer was sawn. As in the case of the lot identifiers in the wafer fabrication factory, starting material wafer manufacturers typically laser mark the surface of each wafer, after sawing and polishing.
As noted above, the laser marking of wafers with identifiers, whether carried out by the wafer fabrication factory or by the manufacturer of the starting material wafers themselves, is conventionally made at the front surface of the wafer (i.e., the surface at which the integrated circuits are to be formed), near an edge so as not to disrupt the formation of integrated circuits thereat. However, the front surface marking of wafers presents numerous problems in the manufacture of integrated circuits.
A first problem with conventional front-surface wafer marking is the lack of visibility of the marking as the wafer is processed to form integrated circuits. The formation of opaque layers, such as metallization, over the wafer identifiers of course obscures the identifiers, except for any topology presented by the identifiers. However, many modern integrated circuit fabrication processes now include planarization of deposited insulator layers prior to the deposition of metallization, in which case even the remaining topology presented by the wafer identifiers is eliminated.
Another readability problem encountered with conventional wafer identifier marking is due to physical boundaries that overlie the marking. For example, many modern wafer fabrication processes utilize a technique referred to as “edge exclusion” to remove excess photoresist that gathers, in the form of a berm, at the perimeter of the wafer because of surface tension effects. Edge exclusion is typically carried out by exposure of the photoresist berms at the wafer edges to light (for positive photoresist) and then dissolution of the exposed photoresist by a solvent. However, if the boundary of the edge exclusion passes over the wafer marking, the readability of the identifier may be significantly reduced by the contrast in structure between the portion in the edge exclusion region and that over which photoresist remains.
Because of these and other limitations, the backside marking of wafers has been considered. However, topology presented by the backside mark has been observed to reduce the ability of vacuum chucks to securely hold the wafer during processing, thus presenting a risk of yield loss. Also, the topology presented by the backside marking has been observed to cause defocus in photolithography. Additionally, integrated circuit wafers are generally thinned by a backgrinding process prior to electrical testing; such backgrinding will, of course, eliminate the wafer identifier.
The reading of conventional wafer marking from either the front or back surfaces, also involves additional wafer movement during wafer fabrication. As is well known in the art, wafers are transported in the wafer fabrication factory by way of multiple-wafer carriers. During such time as wafers are retained within the carrier, frontside or backside wafer markings are not directly visible. The wafers must therefore be translated to be at least partially removed from the carrier in order for human or machine reading of the wafer marking; such translation is of course time consuming in the wafer fabrication factory, involves additional equipment or human intervention, and heightens the risk of wafer damage during manufacture.
By way of further background, special equipment for viewing the surfaces of wafers when in carriers is known, such equipment involving the insertion of mirrors into the space between the wafers in the carrier.
By way of further background, starting material wafer manufacturers also generally construct their wafers to indicate their crystalline orientation, dopant type (p or n), and to provide a registration mark. These indicators are generally in the form of a shaping to the wafer. A common example of such an indicator is the so-called “flat” of the wafer, which is a flat edge formed along a chord of the otherwise circular wafer. In recent years, notches have been formed in the edge of the wafer to provide a registration mark for later processi
Guldi Richard L.
Melcher Keith W.
Williston John
Brady III Wade James
Le Que T.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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