Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-08-30
2003-02-18
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S595000, C257S129000
Reexamination Certificate
active
06521520
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to a semiconductor wafer arrangement and a method of processing a semiconductor wafer, and more particularly to a semiconductor wafer arrangement and a method of processing a semiconductor wafer which inhibits “punch through” and increases the yield of functional semiconductor wafers during the fabrication thereof.
BACKGROUND OF THE INVENTION
Semiconductor wafers are typically fabricated by a layering process in which several layers of material (e.g. a dielectric or an oxide material) are fabricated (i) on a surface of a silicon substrate, or (ii) on a surface of a layer previously disposed on the surface of a silicon substrate. For example, a feature such as a gate can be fabricated on the surface of the silicon substrate. Once the feature is disposed onto the surface of the silicon substrate a layer of an oxide material can also be disposed onto the surface of the substrate material such that the oxide material covers the feature and the surface of the silicon substrate. Once the oxide layer is positioned in the above described manner, the oxide layer is etched so as to form a contact void directly above the feature. In particular, an area of the oxide layer directly over the feature is etched until the etch contacts a top surface of the feature. Since the feature is made from a material which is resistant to the etch (e.g. a dielectric material), the etch stops at the top surface of the feature and thereby creates a contact void through the oxide layer which is located directly above the feature.
However, if the etch area of the oxide layer is not positioned appropriately relative to the feature, for example the etch area is off set relative to the feature rather than being positioned directly over the feature, the etching process can continue past the top surface of the feature and create a defect in the semiconductor wafer commonly known as “punch through”. “Punch through” results in the semiconductor wafer being defective. Creating defective semiconductors wafers by allowing the etch to continue past the top surface of the feature in the above described manner decreases the yield of functional semiconductor wafers obtained from the semiconductor wafer fabrication process.
Thus, a continuing need exists for a semiconductor wafer arrangement and a method of processing a semiconductor wafer which inhibits “punch through” and increases the yield of functional semiconductor wafers during the fabrication thereof.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, there is provided a semiconductor.wafer arrangement. The semiconductor wafer arrangement includes a substrate having a surface. The semiconductor wafer arrangement also includes a feature fabricated from a dielectric material. The feature is attached to the surface such that a first side surface and a second side surface of the feature extend from the surface. The semiconductor wafer arrangement also includes a spacer layer segment positioned in contact with (i) the first side surface of the feature and (ii) the second side surface of the substrate. The semiconductor wafer arrangement further includes a barrier layer segment positioned in contact with (i) the spacer layer segment and (ii) the surface of the substrate so that the spacer layer segment is interposed the first side surface and the barrier layer segment. The semiconductor wafer arrangement further includes an oxide layer positioned in contact with (i) the feature and (ii) the surface of the substrate. The semiconductor wafer arrangement further includes a contact void defined in the oxide layer. The contact void has a first side wall and a second side wall. A space is defined between a first linear extension of the first side surface of the feature and a second linear extension of the second side surface of the feature and the contact void is positioned relative to the feature so that the first side wall of the contact void is located outside of the space.
In accordance with another embodiment of the present invention, there is provided a method of processing a semiconductor wafer which has (i) a substrate, (ii) a surface defined on the substrate, (iii) a feature fabricated from a dielectric material, the feature being attached to the surface such that a first side surface and a second side surface of the feature extend from the surface, (iv) a first spacer layer segment positioned in contact with (A) the first side surface of the feature and (B) the surface of the substrate, (v) a second spacer layer segment positioned in contact with (A) the second side surface of the feature and (B) the surface of the substrate, and (vi) a first isolation trench defined in the surface of the substrate so that the first isolation trench is adjacent to the feature. The method includes (a) disposing a barrier layer onto the surface of the substrate so that the barrier covers the feature and the surface of the substrate and (b) removing the barrier layer from (i) a first area on the surface of the substrate, the first area being interposed the first side surface of the feature and the first isolation trench and (ii) a top surface defined on the feature so as to create a first barrier layer segment positioned in contact with (A) the first spacer layer segment and (B) the surface of the substrate so that the first spacer layer segment is interposed the first side surface of the feature and the first barrier layer segment.
In accordance with still another embodiment of the present invention, there is provided a method of fabricating an electrical device. The method includes (a) providing a semiconductor wafer which has (i) a substrate, (ii) a surface defined on the substrate, (iii) a feature fabricated from a dielectric material, the feature being attached to the surface such that a first side surface and a second side surface of the feature extend from the surface, (iv) a first spacer layer segment positioned in contact with (A) the first side surface of the feature and (B) the surface of the substrate, (v) a second spacer layer segment positioned in contact with (A) the second side surface of the feature and (B) the surface of the substrate, and (vi) a first isolation trench defined in the surface of the substrate so that the first isolation trench is adjacent to the feature, (b) disposing a barrier layer onto the surface of the substrate so that the barrier covers the feature and the surface of the substrate, and (c) removing the barrier layer from (i) a first area on the surface of the substrate, the first area being interposed the first side surface of the feature and the first isolation trench and (ii) a top surface defined on the feature so as to create a first barrier layer segment positioned in contact with (A) the first spacer layer segment and (B) the surface of the substrate so that the first spacer layer segment is interposed the first side surface of the feature and the first barrier layer segment.
It is an object of the present invention to provide a new and useful semiconductor wafer arrangement, method of processing a semiconductor wafer, and method of fabricating an electrical device.
It is an object of the present invention to provide an improved semiconductor wafer arrangement, method of processing a semiconductor wafer, and method of fabricating an electrical device.
It is a further object of the present invention to provide a semiconductor wafer arrangement, a method of processing a semiconductor wafer, and a method of fabricating an electrical device which inhibits “punch through” and increases the yield of functional semiconductor wafers during the fabrication thereof.
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Bhatt Hemanshu
May Charles E.
Cuneo Kamand
Kilday Lisa
LSI Logic Corporation
Maginot, Moore & Bowman LLP
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