Semiconductor wafer and testing method for the same

Details Semiconductor wafer and testing method for the same Semiconductor wafer and testing method for the same

2003-03-12

2004-07-27

Zarneke, David A. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06768332

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor wafer and a method for testing a diced semiconductor wafer.
2. Description of the Related Art
The manufacture of semiconductor integrated circuits includes a multitude of processes including design, manufacture, packaging, and testing. Testing is divided into functional, parametric, and burn-in methodologies. In each of these methodologies, the devices may be tested in wafer, die, or packaged form. Although packaging is a comparatively expensive step, semiconductor manufacturers often package the devices before testing, that is, prior to ensuring proper device operation. The high cost of packaging devices coupled with the increased complexity of the device structures has forced manufacturers to test the devices before packaging, in wafer or die form. By doing so, the probability of packaging malfunctional devices is decreased. Further, with the advent of multichip modules, wafer or die level testing is required since the semiconductor device is only one of several components mounted on a multichip carrier. If one of the semiconductor devices of the multichip module has defects, the whole module would become malfunctional and thus be eliminated. It wastes much manufacturing cost. Therefore, die or wafer level testing is very necessary in such cases.
Generally, integrated circuits are fabricated on semiconductor wafers, and each wafer typically contains between 50 and 1,000 individual integrated circuits. Between the integrated circuits are spaces, known as “street indices”, which separate the individual integrated circuits on the wafer. In a process known as “dicing”, wafers are cut along the street indices to form separate integrated circuits, known as “dice”.
The individual integrated circuits are disposed in an array and arranged regularly; therefore, using wafer level testing can greatly lower the testing time and cost. Currently, semiconductor wafers are tested prior to singulation into individual dice. One of the important reasons is described below. Wafer level testing is typically conducted by using the center of the entire wafer as a fiducial point to position each die. However, there are slight deviations in the coordinates of the dice after the dicing process from the original coordinates of the dice. The slight deviations of individual dice result in big problems during the testing process and cause some of the to-be-tested dice unable to be exactly aligned with the interconnect contacts of a testing machine such that the testing machine can't proceed the testing process or test the dice correctly. But it should be noted that the dicing process is also one of the important causes of damaging the integrated circuits. Since conventional testing processes are conducted prior to the dicing process, only the characteristics and functions of the integrated circuits before the dicing process are verified. However, it can't be judged from the conventional testing processes if the integrated circuits are damaged during the dicing process or not.
Therefore, there exists a need for a testing method that can overcome or at least reduce the aforementioned problems of the prior arts.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for testing a diced wafer thereby overcoming or reducing the position deviation problem of dice due to the dicing process while allowing all of the dice arranged in an array on a wafer to be tested sequentially thereby saving the testing time and expenses thereof.
To achieve the above listed and other objects, the present invention provides a semiconductor wafer comprising a plurality of areas and an array of dice disposed within each of the areas. The present invention is characterized in that at least two fiducial marks are provided in each area of the wafer. According to one embodiment of the present invention, the at least two fiducial marks are disposed in two diagonal corners of each area. The fiducial marks can be patterns in the shape of a cross or other shapes.
The present invention further provides a method for testing a diced wafer. The method comprises the steps as below. First, the surface of a diced wafer is divided into a plurality of areas each including at least two fiducial marks and a plurality of dice each having a plurality of contacts, e.g., bumped contacts. The at least two fiducial marks are not limited to patterns in the shape of a cross or other shapes; alternatively, they may be right-angle edges or circuit features of the dice on the wafer. Next, coordinates of each of the dice within one of the areas is provided by a pattern recognition system through searching and aligning the at least two fiducial marks of the area. After that, interconnect contacts of a prober are placed in electrical communication with the electrical contacts of the dice of the first area according to the obtained coordinates thereof. Thereafter, the pattern recognition system searches and aligns the at least two fiducial marks of any other area thereby obtaining coordinates of the dice within this area of the wafer. In this way, the interconnect contacts of the prober are placed in electrical communication with the electrical contacts of the dice of each area according to the obtained coordinates thereof.
The present invention further provides a method for determining the number of the areas defined on the wafer. Firstly, the surface of a diced wafer is divided into N areas, wherein each area comprises an array of dice and at least two fiducial marks. Next, coordinates of all dice within one of N areas of the diced wafer are provided by a pattern recognition system through searching and aligning the at least two fiducial marks of the area. According to the coordinates obtained in the previous step, interconnect contacts of a prober are moved toward the electrical contacts of the dice; meanwhile, the position deviation between the interconnect contacts of the prober and the electrical contacts of the dice is evaluated. When the position deviation is larger than a predetermined allowable deviation value, the steps of dividing the surface of the diced wafer, obtaining the coordinates and evaluating the position deviation are repeated but the number of the areas is increased at least one at a time until the position deviation obtained in the position deviation evaluating step is smaller than the predetermined allowable deviation value thereby determining that the wafer should be divided into f areas. Therefore, the optimum number of the areas defined on the wafer is f. Thereafter, the dice within each area are tested in the same way as the aforementioned testing method.
The testing method of the present invention not only has the feature of wafer level testing (i.e., testing all of the dice arranged in an array on a wafer), but also has the feature of die level testing to confirm if each die is operational or not thereby obtaining known good dice.
In order to make other objects, advantages, and novel features of the invention become more apparent, detailed description about some preferred embodiment of the present invention will be taken in conjunction with the accompanying drawings as below.


REFERENCES:
patent: 5479109 (1995-12-01), Lau et al.
patent: 5917332 (1999-06-01), Chen et al.
patent: 6480012 (2002-11-01), Komori
patent: 6576529 (2003-06-01), Boulin et al.

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