Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1999-02-19
2001-12-11
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S797000
Reexamination Certificate
active
06329700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor wafer having dicing lines, and a semiconductor device obtained from the wafer.
2. Description of the Background Art
In the manufacture of a semiconductor device, an exposure process is performed a plurality of times. In the exposure process requiring high resolution and accuracy, a mask is aligned by a stepper, using an alignment mark for a stepper previously transferred on a semiconductor wafer. On the other hand, in the exposure process requiring little resolution and accuracy, the mask is aligned by a projection aligner (hereinafter referred to as “PJA”), using an alignment mark for a PJA previously transferred on the semiconductor wafer. In this way, using the stepper and the PJA properly brings improvements in cost and throughput. Thus, concurrent use of the stepper and the PJA has been prevalent. Now, we will give a description of the semiconductor wafer.
FIG. 7
shows a conceptual state of a conventional exposure process. In
FIG. 7
, R
3
is a reticle with patterns CR
31
of sixteen semiconductor element forming regions; D
1
is a region other than the patterns CR
31
, corresponding to a dicing line D which will be described later; X is a lateral direction of a semiconductor wafer W; and Y is a longitudinal direction perpendicular to the lateral direction X. The number of shots on this semiconductor wafer W is 60.
The alignment mark for PJA requires a region corresponding to one or more reticles R
3
. In
FIG. 7
, two regions PM
1
and PM
2
have the alignment mark for PJA. Those regions are arranged in parallel to a plane portion of the edge of the semiconductor wafer W (facet).
FIG. 8
is a partial enlarged plan view of the semiconductor wafer W finally obtained through the exposure process in FIG.
7
and other processes. In
FIG. 8
, D is a dicing line extending straight in the lateral direction X or in the longitudinal direction Y in parallel to others; CR
3
is a semiconductor element forming region with a semiconductor element, sectioned by the dicing lines D; SM
1
and SM
2
are alignment marks for a stepper; and TP is a TEG (Test Element Group) pattern.
The alignment marks SM
1
, SM
2
and the TEG pattern TP are scattered over the dicing lines D which are unavailable regions other than the semiconductor element forming regions CR
3
on the semiconductor wafer W.
The semiconductor element forming regions CR
3
are all in the shape of a square each side of which is L
1
. That is, there is the same interval of L
1
between adjacent dicing lines D (from edge to edge).
Using a dicing device (dicing saw), the semiconductor wafer W is sliced along the dicing lines D to obtain a plurality of chips. The longitudinal size of a chip is shown as L
6
.
The plurality of chips need to be the same in size. This is because chips of different sizes may not be easily mounted on a lead frame at a later assembly process or they may complicate a program of the dicing device.
Further, a blade of the dicing device needs to pass through the center of the dicing lines D. This is to prevent the blade of the dicing device from passing through the semiconductor element forming regions CR
3
due to a mechanical error of the dicing device.
In order to achieve both, i.e., to equalize the chip size and to pass the blade through the center of the dicing lines, the dicing lines D both in the lateral direction X and in the longitudinal direction Y have had the same width Lb as shown in FIG.
8
.
The dicing line is further disclosed in Japanese Patent Laid-Open No. P63-250119A in which every dicing line in the lateral direction has the same width and every dicing line in the longitudinal direction has the same width, but the former width is different from the latter.
The dicing lines, however, need to be wide enough to form the alignment marks SM
1
, SM
2
and the TEG pattern TP thereon. As the width of the dicing lines D increases, an area of the unavailable regions other than the semiconductor element forming regions CR
3
is increased on the semiconductor wafer W. This reduces the number of semiconductor element forming regions CR
3
on the semiconductor wafer W, thereby reducing the number of chips obtained from the single semiconductor wafer W.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor wafer comprising: a plurality of first dicing lines extending in a first direction with a first interval therebetween; a plurality of second dicing lines extending in a second direction with a second interval therebetween, the second direction being orthogonal to the first direction; and a semiconductor element forming region with a semiconductor element, sectioned by the first and the second dicing lines. The plurality of first dicing lines have alternate first and second widths, the second width being larger than the first width.
According to a second aspect of the present invention, in the semiconductor wafer of the first aspect, the plurality of second dicing lines have alternate third and fourth widths, the fourth width being larger than the third width.
According to a third aspect of the present invention, in the semiconductor wafer of the first aspect, the plurality of second dicing lines have the same width smaller than the second width.
According to a fourth aspect of the present invention, in the semiconductor wafer of the first aspect, the first interval equals the second interval.
According to a fifth aspect of the present invention, in the semiconductor wafer of the third aspect, the first interval is longer than the second interval.
According to a sixth aspect of the present invention, the semiconductor wafer of the first aspect further comprises: a pattern used for the manufacturing of a semiconductor device, formed on dicing lines of the maximum width out of the first and the second dicing lines.
A seventh aspect of the present invention is directed to a semiconductor device comprising: a chip obtained by slicing a semiconductor wafer along a plurality of first dicing lines and a plurality of second dicing lines. The semiconductor wafer comprises: the plurality of first dicing lines extending in a first direction with a first interval therebetween; the plurality of second dicing lines extending in a second direction with a second interval therebetween, the second direction being orthogonal to the first direction; and a semiconductor element forming region with a semiconductor element, sectioned by the first and the second dicing lines. The first dicing lines have alternate first and second widths, the second width being larger than the first width.
In the first aspect, unlike the technique disclosed in Japanese Patent laid-Open No. P63-250119A, the first dicing lines have the alternate first and second widths, i.e., first width, second width, first width, second width, first width, . . . . This makes it possible both to equalize the chip size and to pass a blade through the center of the dicing lines, thereby increasing the number of chips obtained from a single semiconductor wafer as compared with the conventional technique. Besides, an alignment mark or a TEG pattern can be formed on the dicing lines of the second width.
In the second aspect, the dicing lines in two-dimensional directions have the alternate widths. This increases the number of chips obtained from a single semiconductor wafer, as compared with the conventional technique.
In the third aspect, the width of the plurality of second dicing lines is narrowed. This increases the number of chips obtained from a single semiconductor wafer.
In the fourth aspect, a larger number of semiconductor element forming regions in the shape of a square can be effectively obtained.
In the fifth aspect, a larger number of semiconductor element forming regions in the shape of a rectangle can be effectively obtained.
In the sixth aspect, the semiconductor wafer can have the pattern to be used for the manufacturing of a semiconductor device, on the dicing lines of the maximum width.
In the sevent
Asano Norihisa
Ishimura Youichi
Takahashi Hideki
Cruz Lourdes
Jackson, Jr. Jerome
Mitsubishi Denki & Kabushiki Kaisha
Oblon, Spivak, McCelland, Maier & Neustadt, P.C.
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