Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-11-20
2003-03-11
Chauduri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S620000, C257S786000
Reexamination Certificate
active
06531709
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor wafer and to methods of making integrated semiconductor chips.
2. Background of the Related Art
FIG. 1
is a plan view of a semiconductor wafer. As shown therein, a plurality of semiconductor chips
12
are formed in the wafer
10
at regular intervals. The wafer
10
is divided into a plurality of semiconductor chips
12
by a cutting process.
FIG. 2
is an enlarged diagram of the circled area shown in FIG.
1
. As shown in
FIG. 2
, chip scribe lanes
14
are formed between the areas of the wafer
10
that will become semiconductor chips
12
. Each of the chip scribe lane
14
has a minimum width that must be maintained so that the semiconductor chip portions are not damaged when the wafer
10
is cut into a plurality of chips
12
. Typically, each chip scribe lane
14
has a width of approximately 150 &mgr;m.
On each of the semiconductor chips
12
, there are a plurality of bonding pads
16
, which may be electrically connected to external pins or leads of a lead frame (not shown). Also, a plurality of wafer probing pads
18
are also formed on each chip
12
. The bonding pads
16
and probing pad to typical have dimensions of approdnately 100 &mgr;m×100 &mgr;m. The wafer probing pads
18
are for testing the semiconductor chip portions of a wafer before the wafer is cut into a plurality of semiconductor chips
12
.
On a background art wafer
10
, both the chip bonding pads
16
and the wafer probing pads
18
are formed on the areas of the wafer
10
corresponding to each of the semiconductor chips
12
. The pads
16
,
18
cannot be made smaller than a predetermined size. This makes it difficult to plan the layout of a highly integrated chip having many bond pads. The more bond pads one attempts to provide on the semiconductor chip, the harder it becomes to fit all the bond pads on the available area. This task is made even more difficult if the chip must also have a plurality of probing pads
18
. Also, in a background art wafer
10
, the wafer probing pads
18
are formed over internal circuits of the semiconductor chips
12
. When a probing tip contacts a probing pad
18
to test a condition of a semiconductor chip, the internal circuits below the probing pad may be affected.
SUMMARY OF THE INVENTION
It is an object to of the present invention to provide a structure of a semiconductor wafer and a fabrication method of a semiconductor chip that obviates at least the problems of the prior art.
It is another object of the present invention to provide where layout area on a chip for bonding pads.
It is another object of the present invention to prevent an internal circuit formed in a semiconductor chip from being damaged during a probing tip test operation.
A semiconductor wafer embodying the invention includes a plurality of semiconductor chips portions provided at regular intervals on the wafer, wherein a plurality of chip bonding pads are formed on each semiconductor chip portion, and a plurality of chip scribe lanes are formed between the semiconductor chip portions. A plurality of wafer probing pads formed on the chip scribe lanes are electrically connected to circuits of the semiconductor chip portions, or corresponding ones of the chip bonding pads. Because the wafer probing pads are provided on the chip scribe lanes, there is more layout area on the chip portions for the bonding pads.
In preferred embodiments of the invention, the chip bonding pads are formed of conductive layers that are electrically connected to metal lines of internal circuits in the semiconductor chips by conductive regions in via holes. The wafer probing pads may be connected to circuits in the chips by conductive layers that extend horizontally into the scribe lanes.
A method of fabricating a semiconductor chip embodying the invention includes the steps of: forming a wafer, wherein a plurality of semiconductor chip portions having internal circuits are disposed at regular intervals on the wafer, and wherein a plurality of chip scribe lanes are formed between the semiconductor chip portions; forming a plurality of chip bonding pads on each of the semiconductor chip portions; forming a plurality of wafer probing pads on the scribe lanes, wherein the wafer probing pads are electrically connected to at least one of internal circuits of the semiconductor chip portion and corresponding ones of the chip bonding pads; and cutting the wafer along the chip scribe lanes to form a plurality of semiconductor chips.
In preferred embodiments of methods according to the present invention, the steps of forming chip bonding pads and wafer probing pads include the sub-steps of: forming a first insulating layer on the wafer; forming via holes in the first insulating layer to expose at least a portion of internal circuits of each of the semiconductor chip portions; forming conductive regions in the via holes; forming conductive layer patterns that are electrically connected to respective ones of the conductive regions in the via holes on the first insulating layer such that each of the conductive layer patterns extends over a portion of a semiconductor chip portion and a portion of a chip scribe lane; forming a second insulating layer on the first insulating layer and the conductive layer patterns; and exposing first portions of the conductive layer patterns on the semiconductor chip portions and second portions of the conductive layer patterns formed on the chip scribe lanes.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
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patent: 5786266 (1998-07-01), Boruta
patent: 5923047 (1999-07-01), Chia et al.
patent: 5982042 (1999-11-01), Nakamura
patent: 6022797 (2000-02-01), Ogasawara et al.
patent: 406085019 (1994-03-01), None
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Kim Jae Woon
Park Jong Hoon
Chauduri Olik
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Pham Hoai
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