Semiconductor wafer

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

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Details

257207, 257210, 257211, 257620, 437 8, H01L 2710

Patent

active

057395462

ABSTRACT:
A semiconductor wafer, having a relatively wide power supply line and ground line, and which can also prevent short-circuiting between these lines. Multiple integrated circuit formation regions, whereon integrated circuits have been formed, are disposed on a semiconductor wafer. A silicon oxide film is formed on a silicon substrate, and a ground line conductor is formed on the silicon oxide film. This ground line conductor is extended over scribe lines. A layer insulation film composed of silicon oxide film is deposited on the silicon oxide film with the ground line conductor interposed therebetween, and a power supply line conductor is formed on the layer insulation film to overlap the ground line conductor. The power supply line conductor is extended over scribe lines. In the integrated circuit formation regions, a power supply pad and the power supply line conductor are electrically connected. A ground pad and the ground line conductor are also electrically connected.

REFERENCES:
patent: 3839781 (1974-10-01), Russell
patent: 5138427 (1992-08-01), Furuyama
patent: 5148263 (1992-09-01), Hamai
patent: 5451801 (1995-09-01), Anderson et al.

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